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847 条记录 (耗时 0.044 秒)

    Undercut insulating regions for silicon-on-insulator device
    141.
    发明授权
    Undercut insulating regions for silicon-on-insulator device 有权
    用于绝缘体上硅器件的底切绝缘区域

    公开(公告)号：US09214378B2

    公开(公告)日：2015-12-15

    申请号：US13537141

    申请日：2012-06-29

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L21/84 ,  H01L21/762 ,  H01L27/12

    CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7838

    摘要： A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

    摘要翻译： 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。

    Semiconductor device with epitaxial source/drain facetting provided at the gate edge
    142.
    发明授权
    Semiconductor device with epitaxial source/drain facetting provided at the gate edge 有权
    具有外延源/漏极平面的半导体器件设置在栅极边缘

    公开(公告)号：US08916443B2

    公开(公告)日：2014-12-23

    申请号：US13534407

    申请日：2012-06-27

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

    IPC分类号： H01L21/8238 ,  H01L27/12 ,  G06F17/50

    CPC分类号： H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/0653

    摘要： A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first spacers are formed on the sidewalls. A raised region is epitaxially grown on the active layer between the adjacent gate structures and at least one trench that extends through the raised region and through the active region is formed, whereby the at least one trench separates the raised region into a first raised region corresponding to a first transistor and a second raised region corresponding to a second transistor. The first raised region and second raised region are electrically isolated by the at least one trench.

    摘要翻译： 形成半导体结构的方法包括提供有源层并在有源层上形成相邻的栅极结构。 栅极结构各自具有侧壁，使得第一间隔件形成在侧壁上。 凸起区域在相邻栅极结构之间的有源层上外延生长，并且形成延伸穿过凸起区域并通过有源区域的至少一个沟槽，由此至少一个沟槽将凸起区域分隔成对应于第一凸起区域 涉及对应于第二晶体管的第一晶体管和第二升高区域。 第一凸起区域和第二凸起区域由至少一个沟槽电隔离。

    Method of multiple patterning to form semiconductor devices
    144.
    发明授权
    Method of multiple patterning to form semiconductor devices 有权
    多重图形化形成半导体器件的方法

    公开(公告)号：US08871596B2

    公开(公告)日：2014-10-28

    申请号：US13555240

    申请日：2012-07-23

    申请人： Kuang-Jung Chen ,  Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Sen Liu

    发明人： Kuang-Jung Chen ,  Kangguo Cheng ,  Bruce B. Doris ,  Steven J. Holmes ,  Sen Liu

    IPC分类号： H01L21/31

    CPC分类号： H01L21/0274 ,  H01L21/26586 ,  H01L21/3081 ,  H01L21/76229 ,  H01L21/76283 ,  H01L29/517 ,  H01L29/66575 ,  H01L29/78

    摘要： A method of forming different structures of a semiconductor device using a single mask and a hybrid photoresist. The method includes: applying a first photoresist layer on a semiconductor substrate; patterning the first photoresist layer using a photomask to form a first patterned photoresist layer; using the first patterned photoresist layer to form a first structure of a semiconductor device; removing the first patterned photoresist layer; applying a second photoresist layer on the semiconductor substrate; patterning the second photoresist layer using the photomask to form a second patterned photoresist layer; using the second patterned photoresist layer to form a second structure of a semiconductor device; removing the second patterned photoresist layer; and wherein either the first or the second photoresist layer is a hybrid photoresist layer comprising a hybrid photoresist.

    摘要翻译： 使用单个掩模和混合光致抗蚀剂形成半导体器件的不同结构的方法。 该方法包括：在半导体衬底上施加第一光致抗蚀剂层; 使用光掩模图案化第一光致抗蚀剂层以形成第一图案化光致抗蚀剂层; 使用所述第一图案化的光致抗蚀剂层形成半导体器件的第一结构; 去除第一图案化光致抗蚀剂层; 在所述半导体衬底上施加第二光致抗蚀剂层; 使用光掩模图案化第二光致抗蚀剂层以形成第二图案化光致抗蚀剂层; 使用所述第二图案化的光致抗蚀剂层形成半导体器件的第二结构; 去除第二图案化光致抗蚀剂层; 并且其中所述第一或第二光致抗蚀剂层是包含混合光致抗蚀剂的混合光致抗蚀剂层。

    Metal gate and high-K dielectric devices with PFET channel SiGe
    146.
    发明授权
    Metal gate and high-K dielectric devices with PFET channel SiGe 有权
    具有PFET通道SiGe的金属栅极和高K电介质器件

    公开(公告)号：US08796773B2

    公开(公告)日：2014-08-05

    申请号：US13539700

    申请日：2012-07-02

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Keith Kwong Hon Wong

    IPC分类号： H01L27/12

    CPC分类号： H01L21/823807 ,  H01L21/823842 ,  H01L21/823857

    摘要： In a circuit structure, PFET devices have a gate dielectric including a high-k dielectric, a gatestack with a metal, a p-source/drain and silicide layer formed over the p-source/drain; NFET devices include a gate dielectric including a high-k dielectric, a gatestack with a metal, an n-source/drain and silicide layer formed over the n-source/drain. An epitaxial SiGe is present underneath and in direct contact with the PFET gate dielectric, while the epitaxial SiGe is absent underneath the NFET gate dielectric.

    摘要翻译： 在电路结构中，PFET器件具有栅极电介质，其包括高k电介质，具有金属的栅格，p源极/漏极和形成在p源极/漏极上的硅化物层; NFET器件包括包括高k电介质的栅极电介质，具有金属的糖饼，在n源极/漏极上形成的n源极/漏极和硅化物层。 外延SiGe存在于PFET栅极电介质的下面并与PFET栅极电介质直接接触，而外延SiGe不存在于NFET栅极电介质下方。

    Semiconductor structure having NFET extension last implants
    150.
    发明授权
    Semiconductor structure having NFET extension last implants 有权
    具有NFET延伸最后植入物的半导体结构

    公开(公告)号：US08673699B2

    公开(公告)日：2014-03-18

    申请号：US13551054

    申请日：2012-07-17

    申请人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

    发明人： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

    IPC分类号： H01L21/00

    CPC分类号： H01L21/84 ,  H01L27/1203

    摘要： A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

    摘要翻译： 一种形成半导体结构的方法，其包括具有PFET部分和NFET部分的极薄的绝缘体上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，邻近 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。 在PFET部分的RSD上形成非晶硅层。 在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的非晶层防止在NFET部分中形成RSD期间在PFET部分中的外延生长。 扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。