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    UNDERCUT INSULATING REGIONS FOR SILICON-ON-INSULATOR DEVICE
    7.
    发明申请
    UNDERCUT INSULATING REGIONS FOR SILICON-ON-INSULATOR DEVICE 有权
    用于绝缘体绝缘体器件的绝缘绝缘区域

    公开(公告)号：US20140001555A1

    公开(公告)日：2014-01-02

    申请号：US13537141

    申请日：2012-06-29

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7838

    摘要： A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

    摘要翻译： 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。

    Undercut insulating regions for silicon-on-insulator device
    8.
    发明授权
    Undercut insulating regions for silicon-on-insulator device 有权
    用于绝缘体上硅器件的底切绝缘区域

    公开(公告)号：US09214378B2

    公开(公告)日：2015-12-15

    申请号：US13537141

    申请日：2012-06-29

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Shom Ponoth ,  Theodorus E. Standaert ,  Tenko Yamashita

    IPC分类号： H01L21/84 ,  H01L21/762 ,  H01L27/12

    CPC分类号： H01L29/0649 ,  H01L21/76229 ,  H01L21/76232 ,  H01L21/76283 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/0653 ,  H01L29/41766 ,  H01L29/78 ,  H01L29/7838

    摘要： A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.

    摘要翻译： 制造绝缘体上硅（SOI）半导体器件的方法包括将底切隔离沟槽蚀刻成SOI衬底，所述SOI衬底包括底部衬底，形成在底部衬底上的掩埋氧化物（BOX）层，以及顶部 SOI层，其形成在BOX层上，其中底切隔离沟槽延伸穿过顶部SOI层和BOX层并进入底部衬底，使得底切绝缘沟槽的一部分位于BOX层下方的底部衬底中。 底切隔离槽填充有包括绝缘材料的底切填充物以形成底切隔离区域。 在与底切隔离区相邻的顶部SOI层上形成场效应晶体管（FET）器件，其中底切隔离区延伸在FET的源极/漏极区的下方。

    Double patterning method
    9.
    发明授权
    Double patterning method 有权
    双重图案化方法

    公开(公告)号：US08889562B2

    公开(公告)日：2014-11-18

    申请号：US13555306

    申请日：2012-07-23

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ying Zhang

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Ying Zhang

    IPC分类号： H01L21/302

    CPC分类号： H01L21/3086 ,  H01B13/00 ,  H01B19/04 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/32134 ,  H01L21/32137

    摘要： Disclosed is an improved double patterning method for forming openings (e.g., vias or trenches) or mesas on a substrate. This method avoids the wafer topography effects seen in prior art double patterning techniques by ensuring that the substrate itself is only subjected to a single etch process. Specifically, in the method, a first mask layer is formed on the substrate and processed such that it has a doped region and multiple undoped regions within the doped region. Then, either the undoped regions or the doped region can be selectively removed in order to form a mask pattern above the substrate. Once the mask pattern is formed, an etch process can be performed to transfer the mask pattern into the substrate. Depending upon whether the undoped regions are removed or the doped region is removed, the mask pattern will form openings (e.g., vias or trenches) or mesas, respectively, on the substrate.

    摘要翻译： 公开了一种用于在基板上形成开口（例如，通孔或沟槽）或台面的改进的双重图案化方法。 该方法通过确保衬底本身仅经历单次蚀刻工艺来避免现有技术的双重图案化技术中所见到的晶片形貌效应。 具体地说，在该方法中，在衬底上形成第一掩模层并进行处理，使得其在掺杂区域内具有掺杂区域和多个未掺杂区域。 然后，可以选择性地去除未掺杂区域或掺杂区域，以在衬底上方形成掩模图案。 一旦形成掩模图案，就可以执行蚀刻工艺以将掩模图案转印到基板中。 取决于未掺杂的区域是去除还是去除掺杂区域，掩模图案将分别在衬底上形成开口（例如，通孔或沟槽）或台面。

    Angle ion implant to re-shape sidewall image transfer patterns
    10.
    发明授权
    Angle ion implant to re-shape sidewall image transfer patterns 有权
    角度离子注入重新形成侧壁图像传输模式

    公开(公告)号：US08343877B2

    公开(公告)日：2013-01-01

    申请号：US12614952

    申请日：2009-11-09

    申请人： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

    发明人： Kangguo Cheng ,  Bruce B. Doris ,  Ying Zhang

    IPC分类号： H01L21/302

    CPC分类号： H01L21/28132 ,  H01L21/26586 ,  H01L29/66787

    摘要： A method for fabrication of features of an integrated circuit and device thereof include patterning a first structure on a surface of a semiconductor device and forming spacers about a periphery of the first structure. An angled ion implantation is applied to the device such that the spacers have protected portions and unprotected portions from the angled ion implantation wherein the unprotected portions have an etch rate greater than an etch rate of the protected portions. The unprotected portions and the first structure are selectively removed with respect to the protected portions. A layer below the protected portions of the spacer is patterned to form integrated circuit features.

    摘要翻译： 一种用于制造集成电路的特征的方法及其装置包括在半导体器件的表面上形成第一结构并在第一结构的周围形成间隔物。 将角度离子注入施加到器件，使得间隔物具有来自成角度离子注入的保护部分和未受保护部分，其中未保护部分具有大于被保护部分的蚀刻速率的蚀刻速率。 相对于受保护部分，非保护部分和第一结构被选择性地去除。 将间隔物的受保护部分下面的层图案化以形成集成电路特征。