公开(公告)号：US11868638B2

公开(公告)日：2024-01-09

申请号：US17018570

申请日：2020-09-11

Applicant: Micron Technology, Inc.

Inventor： Sourabh Dhir ,  Kang-Yong Kim

IPC: G06F12/00 ,  G06F3/06

CPC classification number: G06F3/0647 ,  G06F3/0616 ,  G06F3/0635 ,  G06F3/0653 ,  G06F3/0659 ,  G06F3/0683

Abstract: Methods, systems, and devices for improved inter-memory movement in a multi-memory system are described. A memory device may receive from a host device a command to move data from a first memory controlled by a first controller to a second memory controller by a second controller. The memory device may use the first and second controllers to facilitate the movement of the data from the first memory to the second memory via a path external to the host device. The memory device may indicate to the host device when to suspend activity to the first memory or the second memory and when to resume activity to the first memory or second memory.

公开(公告)号：US20230393748A1

公开(公告)日：2023-12-07

申请号：US17965957

申请日：2022-10-14

Applicant: Micron Technology, Inc.

Inventor： Yang Lu ,  Kang-Yong Kim

IPC: G06F3/06

CPC classification number: G06F3/0613 ,  G06F3/0659 ,  G06F3/0673

Abstract: Systems, apparatuses, and methods related to memory system refresh management are described herein. In an example, a refresh operation can be performed on a set of memory cells in a memory device. The memory device comprising a plurality of sets of memory cells corresponding to respective portions of an array of memory cells of the memory device. The refresh operation can include receiving a mode register write command. The refresh operation can include writing mode register data associated with the mode register write command. The refresh operation can be performed on the set of memory cells at an address location indicated by the written mode register data.

公开(公告)号：US20230343381A1

公开(公告)日：2023-10-26

申请号：US17660199

申请日：2022-04-21

Applicant: Micron Technology, Inc.

Inventor： John Christopher Sancon ,  Yang Lu ,  Kang-Yong Kim ,  Mark Kalei Hadrick ,  Hyun Yoo Lee

IPC: G11C11/406 ,  G11C11/4076 ,  G11C11/408

CPC classification number: G11C11/40618 ,  G11C11/40615 ,  G11C11/4076 ,  G11C11/4085

Abstract: Described apparatuses and methods relate to a bank-level self-refresh for a memory system. A memory device can include logic that implements self-refresh operations in the memory device. The logic may perform self-refresh operations on a set of banks of the memory device that is less than all banks within the memory device. The set of banks of the memory device may be determined such that the peak current in a power distribution network of the memory device is bounded when the self-refresh operation is performed. Accordingly, bank-level self-refresh can reduce a cost of the memory device of a memory system by enabling use of a less complicated power distribution network. The bank-level self-refresh may also be implemented with different types of refresh operations. Amongst other scenarios, bank-level self-refresh can be deployed in memory-expansion environments.

公开(公告)号：US11735246B2

公开(公告)日：2023-08-22

申请号：US17454963

申请日：2021-11-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Atsushi Hatakeyama ,  Hyun Yoo Lee ,  Kang-Yong Kim ,  Akiyoshi Yamamoto

IPC: G11C7/00 ,  G11C11/406

CPC classification number: G11C11/40618 ,  G11C11/40615

Abstract: Disclosed herein is an apparatus that includes a plurality of memory banks and a refresh controller configured to perform a refresh operation on one or more of the plurality of memory banks having a first state without performing the refresh operation on one or more of the plurality of memory banks having a second state responsive to a first refresh command, and perform the refresh operation on a selected one of the plurality of memory banks responsive to a second refresh command. The refresh controller is configured to bring the selected one of the plurality of memory banks into the second state when the refresh operation is performed responsive to the second refresh command.

公开(公告)号：US20230214335A1

公开(公告)日：2023-07-06

申请号：US18149817

申请日：2023-01-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim ,  Dean Gans

IPC: G06F13/16 ,  G11C29/02 ,  G06F9/30 ,  G11C7/22

CPC classification number: G06F13/1689 ,  G11C29/023 ,  G06F9/30145 ,  G11C29/028 ,  G11C7/222

Abstract: Apparatuses and methods including memory commands for semiconductor memories are described. A controller provides a memory system with memory commands to access memory. The commands are decoded to provide internal signals and commands for performing operations, such as operations to access the memory array. The memory commands provided for accessing memory may include timing command and access commands. Examples of access commands include a read command and a write command. Timing commands may be used to control the timing of various operations, for example, for a corresponding access command. The timing commands may include opcodes that set various modes of operation during an associated access operation for an access command.

公开(公告)号：US11475937B2

公开(公告)日：2022-10-18

申请号：US17338458

申请日：2021-06-03

Applicant: Micron Technology, Inc.

Inventor： Taeksang Song ,  Saira S. Malik ,  Hyunyoo Lee ,  Kang-Yong Kim

IPC: G11C11/4074 ,  H01L25/065 ,  H01L27/108 ,  H02M3/156

Abstract: Methods, systems, and devices for die voltage regulation are described. A device may include a first die and second die. A component that generates voltage on the first die may be connected to a capacitor on the second die through a conductive line. The conductive line may allow the capacitor on the second die to regulate voltage generated by the component on the first die.

公开(公告)号：US20220270657A1

公开(公告)日：2022-08-25

申请号：US17668592

申请日：2022-02-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim

IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/156 ,  G11C7/10

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.

公开(公告)号：US20220206717A1

公开(公告)日：2022-06-30

申请号：US17562560

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee ,  Timothy M. Hollis ,  Dong Soon Lim

IPC: G06F3/06

Abstract: Described apparatuses and methods enable communication between a host device and a memory device to establish relative delays between different data lines. If data signals propagate along a bus with the same timing, simultaneous switching output (SSO) and crosstalk can adversely impact channel timing budget parameters. An example system includes an interconnect having multiple data lines that couple the host device to the memory device. In example operations, the host device can transmit to the memory device a command indicative of a phase offset between two or more data lines of the multiple data lines. The memory device can implement the command by transmitting or receiving signals via the interconnect with different relative phase offsets between data lines. The host device (e.g., a memory controller) can determine appropriate offsets for a given apparatus. Lengths of the offsets can vary. Further, a system can activate the phase offsets based on frequency.

公开(公告)号：US20220137881A1

公开(公告)日：2022-05-05

申请号：US17513311

申请日：2021-10-28

Applicant: Micron Technology, Inc.

Inventor： Kang-Yong Kim ,  Hyun Yoo Lee

IPC: G06F3/06

Abstract: Described systems, apparatuses, and methods relate to volatile memories that are refreshed to maintain data integrity, such as dynamic random-access memory (DRAM) and synchronous DRAM (SDRAM). A memory device includes multiple dies, with each die having a memory array to be refreshed. The multiple dies may be interconnected via at least one inter-die bus of the memory device. A memory controller sends a command to the memory device to enter a self-refresh mode. In response, a die of the multiple dies can enter the self-refresh mode and initiate or otherwise coordinate refresh operations of the other dies. To do so, the die may transmit at least one refresh-related command to at least one other die using the inter-die bus. Multiple different signaling schemes and timing approaches are disclosed. The described inter-die refresh control principles may be implemented in energy-efficient applications, such as in low-power double data rate (LPDDR) SDRAM.

公开(公告)号：US11309001B2

公开(公告)日：2022-04-19

申请号：US17071107

申请日：2020-10-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kang-Yong Kim

IPC: G11C7/22 ,  G11C11/4076 ,  H03K5/156 ,  G11C7/10

Abstract: Apparatuses and methods for setting a duty cycler adjuster for improving clock duty cycle are disclosed. The duty cycle adjuster may be adjusted by different amounts, at least one smaller than another. Determining when to use the smaller adjustment may be based on duty cycle results. A duty cycle monitor may have an offset. A duty cycle code for the duty cycle adjuster may be set to an intermediate value of a duty cycle monitor offset. The duty cycle monitor offset may be determined by identifying duty cycle codes for an upper and for a lower boundary of the duty cycle monitor offset.