公开(公告)号：US08859425B2

公开(公告)日：2014-10-14

申请号：US13652033

申请日：2012-10-15

Applicant: Micron Technology, Inc.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/768

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/014

Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more openings in a front side of the semiconductor device and forming sacrificial plugs in the openings that partially fill the openings. The method further includes further filling the partially filled openings with a conductive material, where individual sacrificial plugs are generally between the conductive material and a substrate of the semiconductor device. The sacrificial plugs are exposed at a backside of the semiconductor device. Contact regions can be formed at the backside by removing the sacrificial plugs.

Abstract translation: 本文公开了制造半导体器件的方法。 根据特定实施例配置的方法包括在半导体器件的前侧形成一个或多个开口，并且在部分填充开口的开口中形成牺牲塞。 该方法还包括用导电材料进一步填充部分填充的开口，其中各个牺牲插塞通常在导电材料和半导体器件的衬底之间。 牺牲插头暴露在半导体器件的背面。 可以通过去除牺牲塞在背面形成接触区域。

公开(公告)号：US20140217498A1

公开(公告)日：2014-08-07

申请号：US14247968

申请日：2014-04-08

Applicant: Micron Technology, Inc.

Inventor： Jasper S. Gibbons ,  Darren V. Young ,  Kunal R. Parekh ,  Casey Smith

IPC: H01L29/423 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L21/823425 ,  H01L21/82345 ,  H01L29/407 ,  H01L29/66621 ,  H01L29/7831

Abstract: Recessed access transistor devices used with semiconductor devices may include gate electrodes having materials with multiple work functions, materials that are electrically isolated from each other and supplied with two or more voltage supplies, or materials that create a diode junction within the gate electrode.

Abstract translation: 与半导体器件一起使用的嵌入式晶体管器件可以包括具有多个功函数材料的栅电极，彼此电隔离并且被提供有两个或多个电压源的材料，或者在栅电极内产生二极管结的材料。

公开(公告)号：US20140217350A1

公开(公告)日：2014-08-07

申请号：US13761570

申请日：2013-02-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Jun Liu ,  Kunal R. Parekh

IPC: H01L45/00

CPC classification number: H01L27/2463 ,  H01L27/2409 ,  H01L45/06 ,  H01L45/065 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1683

Abstract: An array of memory cells includes buried access lines having conductively doped semiconductor material. Pillars extend elevationally outward of and are spaced along the buried access lines. The pillars individually include a memory cell. Outer access lines are elevationally outward of the pillars and the buried access lines. The outer access lines are of higher electrical conductivity than the buried access lines. A plurality of conductive vias is spaced along and electrically couple pairs of individual of the buried and outer access lines. A plurality of the pillars is between immediately adjacent of the vias along the pairs. Electrically conductive metal material is directly against tops of the buried access lines and extends between the pillars along the individual buried access lines. Other embodiments, including method, are disclosed.

Abstract translation: 存储单元阵列包括具有导电掺杂半导体材料的掩埋访问线。 支柱向外延伸并沿着掩埋的进入管线间隔开。 支柱分别包括一个记忆单元。 外部接入线在柱子和埋入式接入线路的正上方。 外部接入线路比埋入式接入线路的导电性高。 多个导电通孔沿着并且电耦合埋入和外部接入线路中的各个对间隔开。 多个支柱在沿对之间的通孔的紧邻之间。 导电金属材料直接抵靠埋入式接入线路的顶部，并沿独立的埋入式接入线路在支柱之间延伸。 公开了包括方法的其它实施例。

公开(公告)号：US20140103520A1

公开(公告)日：2014-04-17

申请号：US13652033

申请日：2012-10-15

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kyle K. Kirby ,  Kunal R. Parekh

IPC: H01L21/768 ,  H01L23/498 ,  H01L23/48

CPC classification number: H01L23/49827 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/49811 ,  H01L24/05 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/0557 ,  H01L2224/13025 ,  H01L2224/131 ,  H01L2924/014

Abstract: Methods for making semiconductor devices are disclosed herein. A method configured in accordance with a particular embodiment includes forming one or more openings in a front side of the semiconductor device and forming sacrificial plugs in the openings that partially fill the openings. The method further includes further filling the partially filled openings with a conductive material, where individual sacrificial plugs are generally between the conductive material and a substrate of the semiconductor device. The sacrificial plugs are exposed at a backside of the semiconductor device. Contact regions can be formed at the backside by removing the sacrificial plugs.

Abstract translation: 本文公开了制造半导体器件的方法。 根据特定实施例配置的方法包括在半导体器件的前侧形成一个或多个开口，并且在部分填充开口的开口中形成牺牲塞。 该方法还包括用导电材料进一步填充部分填充的开口，其中各个牺牲插塞通常在导电材料和半导体器件的衬底之间。 牺牲插头暴露在半导体器件的背面。 可以通过去除牺牲塞在背面形成接触区域。

公开(公告)号：US08669603B2

公开(公告)日：2014-03-11

申请号：US14010444

申请日：2013-08-26

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L27/108

CPC classification number: H01L29/78 ,  H01L21/84 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10805 ,  H01L27/10873 ,  H01L27/1207 ,  H01L29/0603 ,  H01L29/7841

Abstract: Some embodiments include DRAM having transistor gates extending partially over SOI, and methods of forming such DRAM. Unit cells of the DRAM may be within active region pedestals, and in some embodiments the unit cells may comprise capacitors having storage nodes in direct contact with sidewalls of the active region pedestals. Some embodiments include 0C1T memory having transistor gates entirely over SOI, and methods of forming such 0C1T memory.

Abstract translation: 一些实施例包括具有在SOI上部分延伸的晶体管栅极的DRAM以及形成这种DRAM的方法。 DRAM的单位单元可以在有源区域基座内，并且在一些实施例中，单位单元可以包括具有与有源区域基座的侧壁直接接触的存储节点的电容器。 一些实施例包括具有完全在SOI上的晶体管栅极的OC1T存储器，以及形成这种0C1T存储器的方法。

公开(公告)号：US20250151274A1

公开(公告)日：2025-05-08

申请号：US19013909

申请日：2025-01-08

Applicant: Micron Technology, Inc.

Inventor： Hongbin Zhu ,  Gurtej S. Sandhu ,  Kunal R. Parekh

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/30 ,  H10B43/30 ,  H10B43/35 ,  H10B43/40 ,  H10B99/00

Abstract: A method used in forming a vertical string of memory cells and a conductive via comprises forming a first lower opening and a second lower opening into a lower material. A first material is formed within the first and second lower openings. An upper material is formed above the lower material and above the first material in the first and second lower openings. A first upper opening is formed through the upper material to the first material in the first lower opening. At least a majority of the first material is removed from the first lower opening through the first upper opening and channel material is formed within the first lower and first upper openings for the vertical string of memory cells being formed. After forming the channel material, a second upper opening is formed through the upper material to the first material in the second lower opening. Conductive material of the conductive via is formed within the second upper opening. Structure embodiments independent of method of formation are disclosed.

公开(公告)号：US20250140756A1

公开(公告)日：2025-05-01

申请号：US19005309

申请日：2024-12-30

Applicant: Micron Technology, Inc.

Inventor： Wei Zhou ,  Kyle K. Kirby ,  Bret K. Street ,  Kunal R. Parekh

IPC: H01L25/065 ,  H01L25/00

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor die and a molding material. The semiconductor die may have a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein. The molding material may be laterally adjacent to the semiconductor die.

公开(公告)号：US20250098169A1

公开(公告)日：2025-03-20

申请号：US18966391

申请日：2024-12-03

Applicant: Micron Technology, Inc.

Inventor： Justin B. Dorhout ,  David Daycock ,  Kunal R. Parekh ,  Martin C. Roberts ,  Yushi Hu

IPC: H10B43/27 ,  H01L29/66 ,  H01L29/76 ,  H01L29/78

Abstract: Some embodiments include an integrated structure having a conductive material, a select device gate material over the conductive material, and vertically-stacked conductive levels over the select device gate material. Vertically-extending monolithic channel material is adjacent the select device gate material and the conductive levels. The monolithic channel material contains a lower segment adjacent the select device gate material and an upper segment adjacent the conductive levels. A first vertically-extending region is between the lower segment of the monolithic channel material and the select device gate material. The first vertically-extending region contains a first material. A second vertically-extending region is between the upper segment of the monolithic channel material and the conductive levels. The second vertically-extending region contains a material which is different in composition from the first material.

公开(公告)号：US20250081460A1

公开(公告)日：2025-03-06

申请号：US18745922

申请日：2024-06-17

Applicant: Micron Technology, Inc.

Inventor： Albert Fayrushin ,  Haitao Liu ,  Kunal R. Parekh

IPC: H10B43/27 ,  H10B41/27 ,  H10B41/35 ,  H10B43/35

Abstract: A microelectronic device includes a stack structure, a cell pillar structure, doped semiconductor material, and control logic devices. The stack structure includes vertically neighboring tiers respectively including a conductive structure and an insulative structure vertically neighboring the conductive structure. The cell pillar structure vertically extends through the stack structure and includes a fill material, a channel material horizontally surrounding the fill material, and an outer material stack horizontally surrounding the channel material. The doped semiconductor material vertically overlies the stack structure and includes a first portion substantially continuously horizontally extending over the stack structure and the cell pillar structure, and a second portion vertically projecting from the first portion and in physical contact with the channel material of the cell pillar structure. The control logic devices vertically underlie and are coupled to the cell pillar structures. Related methods, memory devices, and electronic systems are also described.

公开(公告)号：US12205846B2

公开(公告)日：2025-01-21

申请号：US18333235

申请日：2023-06-12

Applicant: Micron Technology, Inc.

Inventor： Kunal R. Parekh

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H10B41/27 ,  H10B43/27

Abstract: A method of forming a microelectronic device comprises forming line structures comprising conductive material and insulative material overlying the conductive material, the line structures separated from one another by trenches. An isolation material is formed on surfaces of the line structures inside and outside of the trenches, the isolation material only partially filling the trenches to form air gaps interposed between the line structures. Openings are formed to extend through the isolation material and expose portions of the insulative material of the line structures. The exposed portions of the insulative material of the line structures are removed to form extended openings extending to the conductive material of the line structures. Conductive contact structures are formed within the extended openings. Conductive pad structures are formed on the conductive contact structures. Additional methods, microelectronic devices, memory devices, and electronic systems are also described.