公开(公告)号：US08993384B2

公开(公告)日：2015-03-31

申请号：US13913511

申请日：2013-06-09

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chung-Fu Chang ,  Cheng-Guo Chen ,  Chien-Ting Lin

IPC: H01L21/00 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8234

CPC classification number: H01L29/7851 ,  H01L21/8234 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/161 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/7848 ,  H01L29/7855

Abstract: A semiconductor device includes a fin structure, an isolation structure, a gate structure and an epitaxial structure. The fin structure protrudes from the surface of the substrate and includes a top surface and two sidewalls. The isolation structure surrounds the fin structure. The gate structure overlays the top surface and the two sidewalls of a portion of the fin structure, and covers a portion of the isolation structure. The isolation structure under the gate structure has a first top surface and the isolation structure at two sides of the gate structure has a second top surface, wherein the first top surface is higher than the second top surface. The epitaxial layer is disposed at one side of the gate structure and is in direct contact with the fin structure.

Abstract translation: 半导体器件包括鳍结构，隔离结构，栅极结构和外延结构。 翅片结构从衬底的表面突出并且包括顶表面和两个侧壁。 隔离结构围绕翅片结构。 栅极结构覆盖鳍结构的一部分的顶表面和两个侧壁，并且覆盖隔离结构的一部分。 栅极结构下的隔离结构具有第一顶表面，并且栅极结构两侧的隔离结构具有第二顶表面，其中第一顶表面高于第二顶表面。 外延层设置在栅极结构的一侧并与鳍结构直接接触。

公开(公告)号：US08981487B2

公开(公告)日：2015-03-17

申请号：US13954991

申请日：2013-07-31

Applicant: United Microelectronics Corp.

Inventor： Yu-Hsiang Hung ,  Ssu-I Fu ,  Chien-Ting Lin ,  Po-Chao Tsao ,  Chung-Fu Chang ,  Cheng-Guo Chen

IPC: H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/1211 ,  H01L21/845

Abstract: A method for fabricating fin-shaped field-effect transistor (FinFET) is disclosed. The method includes the steps of: providing a substrate; forming a fin-shaped structure in the substrate; forming a shallow trench isolation (STI) on the substrate and around the bottom portion of the fin-shaped structure; forming a first gate structure on the STI and the fin-shaped structure; and removing a portion of the STI for exposing the sidewalls of the STI underneath the first gate structure.

Abstract translation: 公开了一种用于制造鳍状场效应晶体管（FinFET）的方法。 该方法包括以下步骤：提供衬底; 在基板中形成翅片状结构; 在衬底上并在鳍状结构的底部周围形成浅沟槽隔离（STI）; 在STI和鳍状结构上形成第一栅极结构; 以及去除STI的一部分以暴露在第一栅极结构下方的STI的侧壁。

公开(公告)号：US20140349482A1

公开(公告)日：2014-11-27

申请号：US13902970

申请日：2013-05-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Chao Tsao ,  Chien-Ting Lin

IPC: H01L21/306 ,  H01L21/311 ,  H01L21/304

CPC classification number: H01L21/3086 ,  H01L21/76224 ,  H01L29/66795

Abstract: A method of forming fin-shaped structures includes the following steps. A plurality of spacers is formed on a substrate. The substrate is etched by using the spacers as hard masks to form a plurality of fin-shaped structures in the substrate. A cutting process is then performed to remove parts of the fin-shaped structures and the spacers formed on the removed parts.

Abstract translation: 形成鳍状结构的方法包括以下步骤。 在基板上形成多个间隔物。 通过使用间隔物作为硬掩模来蚀刻衬底，以在衬底中形成多个鳍状结构。 然后进行切割过程以去除鳍状结构的部分和形成在去除部分上的间隔物。

公开(公告)号：US20140327055A1

公开(公告)日：2014-11-06

申请号：US13886382

申请日：2013-05-03

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Jun-Jie Wang ,  Po-Chao Tsao ,  Chia-Jui Liang ,  Shih-Fang Tzou ,  Chien-Ting Lin ,  Cheng-Guo Chen ,  Ssu-I Fu ,  Yu-Hsiang Hung ,  Chung-Fu Chang

IPC: H01L21/28 ,  H01L29/40

CPC classification number: H01L29/42364 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/7851

Abstract: A replacement gate process is disclosed. A substrate and a dummy gate structure formed on the substrate is provided, wherein the dummy gate structure comprises a dummy layer on the substrate, a hard mask layer on the dummy layer, spacers at two sides of the dummy layer and the hard mask layer, and a contact etch stop layer (CESL) covering the substrate, the spacers and the hard mask layer. The spacers and the CESL are made of the same material. Then, a top portion of the CESL is removed to expose the hard mask layer. Next, the hard mask layer is removed. Afterward, the dummy layer is removed to form a trench.

Abstract translation: 公开了替代浇口工艺。 提供了一种在基板上形成的基板和虚拟栅极结构，其中，虚设栅极结构包括基板上的虚设层，虚设层上的硬掩模层，虚设层两侧的间隔物和硬掩模层， 以及覆盖衬底，间隔物和硬掩模层的接触蚀刻停止层（CESL）。 垫片和CESL由相同的材料制成。 然后，去除CESL的顶部以露出硬掩模层。 接下来，去除硬掩模层。 之后，去除虚拟层以形成沟槽。

公开(公告)号：US20140199817A1

公开(公告)日：2014-07-17

申请号：US14219010

申请日：2014-03-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Chien-Liang Lin ,  Chien-Ting Lin ,  Ssu-I Fu ,  Ying-Tsung Chen

IPC: H01L29/66

CPC classification number: H01L29/66795

Abstract: A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.

Abstract translation: 一种制造多栅极晶体管器件的方法包括：提供具有图案化半导体层，栅极电介质层和顺序地形成在其上的栅极层的半导体衬底，形成依次具有第一绝缘层和第二绝缘层的覆盖层 图案化半导体层和栅极层，去除多个绝缘层的一部分以同时在栅极层周围形成第一间隔物，以及围绕图案化半导体层形成第二间隔物，去除第二间隔物以暴露第一绝缘层的一部分 覆盖图案化的半导体层并且同时移除第一间隔物的一部分以形成围绕栅极层的第三间隔物，以及去除暴露的第一绝缘层以暴露图案化的半导体层。

公开(公告)号：US20140127892A1

公开(公告)日：2014-05-08

申请号：US14135520

申请日：2013-12-19

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Po-Jui Liao ,  Tsung-Lung Tsai ,  Chien-Ting Lin ,  Shao-Hua Hsu ,  Yeng-Peng Wang ,  Chun-Hsien Lin ,  Chan-Lon Yang ,  Guang-Yaw Hwang ,  Shin-Chi Chen ,  Hung-Ling Shih ,  Jiunn-Hsiung Liao ,  Chia-Wen Liang

IPC: H01L21/8238

CPC classification number: H01L29/78 ,  H01L21/823842 ,  H01L21/82385 ,  H01L29/66545

Abstract: A method of manufacturing a semiconductor device having metal gate includes providing a substrate having a first transistor and a second transistor formed thereon, the first transistor having a first gate trench formed therein, forming a first work function metal layer in the first gate trench, forming a sacrificial masking layer in the first gate trench, removing a portion of the sacrificial masking layer to expose a portion of the first work function metal layer, removing the exposed first function metal layer to form a U-shaped work function metal layer in the first gate trench, and removing the sacrificial masking layer. The first transistor includes a first conductivity type and the second transistor includes a second conductivity type. The first conductivity type and the second conductivity type are complementary.

Abstract translation: 一种制造具有金属栅极的半导体器件的方法包括：提供具有形成在其上的第一晶体管和第二晶体管的衬底，所述第一晶体管具有形成在其中的第一栅极沟槽，在所述第一栅极沟槽中形成第一功函数金属层， 在第一栅极沟槽中的牺牲掩模层，去除牺牲掩模层的一部分以暴露第一功函数金属层的一部分，去除暴露的第一功能金属层，以在第一栅极沟槽中的第一栅极沟槽中形成U形功函数金属层 栅极沟槽，以及去除牺牲掩模层。 第一晶体管包括第一导电类型，第二晶体管包括第二导电类型。 第一导电类型和第二导电类型是互补的。

公开(公告)号：US20140077229A1

公开(公告)日：2014-03-20

申请号：US14089771

申请日：2013-11-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： An-Chi Liu ,  Chun-Hsien Lin ,  Yu-Cheng Tung ,  Chien-Ting Lin ,  Wen-Tai Chiang ,  Shih-Hung Tsai ,  Ssu-I Fu ,  Ying-Tsung Chen ,  Chih-Wei Chen

IPC: H01L29/78 ,  H01L29/786

CPC classification number: H01L29/7834 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654

Abstract: A non-planar semiconductor structure comprises a substrate, at least one fin structure on the substrate, a gate covering parts of the fin structures and part of the substrate such that the fin structure is divided into a channel region stacking with the gate and source/drain region at both sides of the gate, a plurality of epitaxial structures covering on the source/drain region of the fin structures, a recess is provided between the channel region of the fin structure and the epitaxial structure, and a spacer formed on the sidewalls of the gate and the epitaxial structures, wherein the portion of the spacer filling in the recesses is flush with the top surface of the epitaxial structures.

Abstract translation: 非平面半导体结构包括衬底，衬底上的至少一个翅片结构，鳍覆盖部分的鳍结构和衬底的一部分，使得鳍结构被分成与栅极和源极/漏极堆叠的沟道区域， 漏极区域，覆盖在鳍状结构的源极/漏极区域上的多个外延结构，在鳍状结构的沟道区域和外延结构之间设置凹部，以及形成在侧壁上的间隔物 的栅极和外延结构，其中填充在凹槽中的间隔物的部分与外延结构的顶表面齐平。

公开(公告)号：US20130228836A1

公开(公告)日：2013-09-05

申请号：US13869037

申请日：2013-04-24

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Shih-Hung Tsai ,  Chien-Ting Lin ,  Chin-Cheng Chien ,  Chin-Fu Lin ,  Chih-Chien Liu ,  Teng-Chun Tsai ,  Chun-Yuan Wu

IPC: H01L29/78

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A non-planar semiconductor structure includes a substrate, at least two fin-shaped structures, at least an isolation structure, and a plurality of epitaxial layers. The fin-shaped structures are located on the substrate. The isolation structure is located between the fin-shaped structures, and the isolation structure has a nitrogen-containing layer. The epitaxial layers respectively cover a part of the fin-shaped structures and are located on the nitrogen-containing layer. Anon-planar semiconductor process is also provided for forming the semiconductor structure.

Abstract translation: 非平面半导体结构包括衬底，至少两个鳍状结构，至少一个隔离结构和多个外延层。 鳍状结构位于基底上。 隔离结构位于鳍状结构之间，隔离结构具有含氮层。 外延层分别覆盖了鳍状结构的一部分并且位于含氮层上。 还提供了用于形成半导体结构的非平面半导体工艺。