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    Semiconductor process
    1.
    发明授权
    Semiconductor process 有权
    半导体工艺

    公开(公告)号：US09449829B1

    公开(公告)日：2016-09-20

    申请号：US14705960

    申请日：2015-05-06

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Yu-Tung Hsiao ,  Chien-Liang Lin ,  Yu-Ren Wang

    IPC分类号： H01L21/28 ,  H01L29/51 ,  H01L29/49

    CPC分类号： H01L29/4966 ,  H01L21/28088 ,  H01L21/28202 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545

    摘要： A semiconductor process includes the following steps. A dielectric layer is formed on a substrate. A barrier layer is formed on the dielectric layer. An ammonia thermal treatment process with a processing temperature of 650° C.˜700° C. and a nitrogen containing gas annealing process with a processing temperature of 900° C.˜1000° C. are sequentially performed on the barrier layer. The present invention also provides a semiconductor process including the following steps. A dielectric layer is formed on a substrate. A first nitrogen containing thermal treatment process is performed on the dielectric layer. A barrier layer is formed on the dielectric layer. A second nitrogen containing thermal treatment process and then an annealing process are performed in-situ on the barrier layer.

    摘要翻译： 半导体工艺包括以下步骤。 在基板上形成电介质层。 在电介质层上形成阻挡层。 在阻挡层上依次进行处理温度为650℃〜700℃的氨热处理工序和处理温度为900℃〜1000℃的含氮气体退火处理。 本发明还提供一种包括以下步骤的半导体工艺。 在基板上形成电介质层。 在介电层上进行第一含氮热处理工艺。 在电介质层上形成阻挡层。 在阻挡层上原位进行第二种含氮热处理工艺，然后进行退火处理。

    POLYSILICON LAYER
    2.
    发明申请
    POLYSILICON LAYER 审中-公开
    多晶硅层

    公开(公告)号：US20150021776A1

    公开(公告)日：2015-01-22

    申请号：US14507317

    申请日：2014-10-06

    申请人： United Microelectronics Corp.

    发明人： Chien-Liang Lin ,  Yu-Ren Wang ,  Ying-Wei Yen ,  Wen-Yi Teng ,  Chan-Lon Yang

    IPC分类号： H01L29/49

    CPC分类号： H01L29/4916 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/28035 ,  H01L29/4925

    摘要： A polysilicon layer including an amorphous polysilicon layer and a crystallized polysilicon layer is provided. The crystallized polysilicon layer is disposed on the amorphous polysilicon layer. Besides, the amorphous polysilicon layer has a first grain size, the crystallized polysilicon layer has a second grain size, and the first grain size is smaller than the second grain size. The amorphous polysilicon layer with a smaller grain size can serve as a base for the following deposition, so that the crystallized polysilicon layer formed thereon has a flatter topography, and thus, the surface roughness is reduced and the Rs uniformity within a wafer is improved.

    摘要翻译： 提供了包括非晶多晶硅层和结晶的多晶硅层的多晶硅层。 结晶的多晶硅层设置在非晶多晶硅层上。 此外，非晶多晶硅层具有第一晶粒尺寸，结晶的多晶硅层具有第二晶粒尺寸，并且第一晶粒尺寸小于第二晶粒尺寸。 具有较小晶粒尺寸的非晶多晶硅层可以用作随后沉积的基底，使得其上形成的结晶多晶硅层具有更平坦的形貌，因此表面粗糙度降低，晶片内的Rs均匀性提高。

    METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE
    5.
    发明申请
    METHOD FOR MANUFACTURING MULTI-GATE TRANSISTOR DEVICE 审中-公开
    制造多栅极晶体管器件的方法

    公开(公告)号：US20140199817A1

    公开(公告)日：2014-07-17

    申请号：US14219010

    申请日：2014-03-19

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Shih-Hung Tsai ,  Chien-Liang Lin ,  Chien-Ting Lin ,  Ssu-I Fu ,  Ying-Tsung Chen

    IPC分类号： H01L29/66

    CPC分类号： H01L29/66795

    摘要： A method for manufacturing multi-gate transistor device includes providing a semiconductor substrate having a patterned semiconductor layer, a gate dielectric layer and a gate layer sequentially formed thereon, forming a multiple insulating layer sequentially having a first insulating layer and a second insulating layer and covering the patterned semiconductor layer and the gate layer, removing a portion of the multiple insulating layer to simultaneously form a first spacer around the gate layer and a second spacer around the patterned semiconductor layer, removing the second spacer to expose a portion of the first insulating layer covering the patterned semiconductor layer and simultaneously removing a portion of the first spacer to form a third spacer around the gate layer, and removing the exposed first insulating layer to expose the patterned semiconductor layer.

    摘要翻译： 一种制造多栅极晶体管器件的方法包括：提供具有图案化半导体层，栅极电介质层和顺序地形成在其上的栅极层的半导体衬底，形成依次具有第一绝缘层和第二绝缘层的覆盖层 图案化半导体层和栅极层，去除多个绝缘层的一部分以同时在栅极层周围形成第一间隔物，以及围绕图案化半导体层形成第二间隔物，去除第二间隔物以暴露第一绝缘层的一部分 覆盖图案化的半导体层并且同时移除第一间隔物的一部分以形成围绕栅极层的第三间隔物，以及去除暴露的第一绝缘层以暴露图案化的半导体层。

    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF
    6.
    发明申请
    SEMICONDUCTOR STRUCTURE AND PROCESS THEREOF 有权
    半导体结构及其工艺

    公开(公告)号：US20140159211A1

    公开(公告)日：2014-06-12

    申请号：US13710382

    申请日：2012-12-10

    申请人： UNITED MICROELECTRONICS CORP.

    发明人： Chien-Liang Lin ,  Yu-Ren Wang ,  Ying-Wei Yen

    IPC分类号： H01L21/02 ,  H01L21/441 ,  H01L29/06

    CPC分类号： H01L21/28185 ,  H01L21/02164 ,  H01L21/02332 ,  H01L21/02337 ,  H01L21/0234 ,  H01L21/28202 ,  H01L21/3105 ,  H01L21/31155 ,  H01L21/441 ,  H01L29/0603 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/78

    摘要： A semiconductor structure includes a dielectric layer located on a substrate, wherein the dielectric layer includes nitrogen atoms, and the concentration of the nitrogen atoms in the dielectric layer is lower than 5% at a location wherein the distance between this location in the dielectric layer to the substrate is less than 20% of the thickness of the dielectric layer. Moreover, the present invention provides a semiconductor process including the following steps: a dielectric layer is formed on a substrate. Two annealing processes are performed in-situly on the dielectric layer, wherein the two annealing processes have different imported gases and different annealing temperatures.

    摘要翻译： 半导体结构包括位于基板上的电介质层，其中介电层包括氮原子，并且介电层中氮原子的浓度低于5％，其中介电层中该位置之间的距离与 基板的厚度小于电介质层厚度的20％。 此外，本发明提供一种包括以下步骤的半导体工艺：在基板上形成电介质层。 在电介质层上进行两个退火工艺，其中两个退火工艺具有不同的进口气体和不同的退火温度。