公开(公告)号：US10593865B2

公开(公告)日：2020-03-17

申请号：US15904429

申请日：2018-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L27/22 ,  H01L43/02 ,  H01L43/08 ,  H01L43/12

Abstract: A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug.

公开(公告)号：US20190273117A1

公开(公告)日：2019-09-05

申请号：US16297698

申请日：2019-03-10

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Ching-Wen Hung ,  Yu-Ping Wang

IPC: H01L27/22 ,  G11C11/16 ,  H01F41/34 ,  H01F10/32 ,  H01L43/12 ,  H01L23/522 ,  H01L43/08 ,  H01L23/528 ,  H01L43/02

Abstract: A semiconductor device and method of forming the same, the semiconductor device includes a substrate, first plug, a magnetoresistive random access memory (MRAM) structure, a spacer layer, a seal layer and a first conductive pattern. The substrate has a first region and a second region, and the first plug is disposed on a dielectric layer disposed on the substrate, within the first region. The MRAM structure is disposed in the dielectric layer and electrically connected to the first plug. The spacer layer is disposed both within the first region and the second region, to cover the MRAM structure. The seal layer is disposed on the MRAM structure and the first plug, only within the first region. The first conductive pattern penetrates through the seal layer to electrically connect the MRAM structure.

公开(公告)号：US20190237660A1

公开(公告)日：2019-08-01

申请号：US15904429

申请日：2018-02-26

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hung-Chan Lin ,  Yu-Ping Wang ,  Hung-Yueh Chen

IPC: H01L43/02 ,  H01L43/12 ,  H01L43/08 ,  H01L27/22

Abstract: A magnetoresistive random access memory (MRAM) is provided in the present invention, including a conductive plug with a protruding portion extending outwardly on one side and a notched portion concaving inwardly on the other side of the upper edge of conductive plug, and a memory cell with a bottom electrode electrically connecting with the conductive plug, a magnetic tunnel junction (MTJ) on the bottom electrode, and a top electrode on the magnetic tunnel junction, wherein the bottom surface of memory cell completely overlaps the top surface of conductive plug.

公开(公告)号：US20160093616A1

公开(公告)日：2016-03-31

申请号：US14526552

申请日：2014-10-29

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chien-Ming Lai ,  Chien-Chung Huang ,  Yu-Ting Tseng ,  Ya-Huei Tsai ,  Yu-Ping Wang

IPC: H01L27/092 ,  H01L29/49 ,  H01L21/28 ,  H01L21/8238

CPC classification number: H01L21/823437 ,  H01L21/28088 ,  H01L21/283 ,  H01L21/3211 ,  H01L21/32139 ,  H01L21/823842 ,  H01L27/092 ,  H01L27/0922 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7843

Abstract: The present invention provides a complementary metal oxide semiconductor device, comprising a PMOS and an NMOS. The PMOS has a P type metal gate, which comprises a bottom barrier layer, a P work function metal (PWFM) layer, an N work function tuning (NWFT) layer, an N work function metal (NWFM) layer and a metal layer. The NMOS has an N type metal gate, which comprises the NWFT layer, the NWFM layer and the low-resistance layer. The present invention further provides a method of forming the same.

Abstract translation: 本发明提供一种互补金属氧化物半导体器件，其包括PMOS和NMOS。 PMOS具有P型金属栅极，其包括底部阻挡层，P功函数金属（PWFM）层，N功函数调整（NWFT）层，N功函数金属（NWFM）层和金属层。 NMOS具有N型金属栅极，其包括NWFT层，NWFM层和低电阻层。 本发明还提供一种形成该方法的方法。

公开(公告)号：US12274180B2

公开(公告)日：2025-04-08

申请号：US18122730

申请日：2023-03-17

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen-Yi Weng ,  Si-Han Tsai ,  Che-Wei Chang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Ju-Chun Fan ,  Ching-Hua Hsu ,  Yi-Yu Lin ,  Hung-Yueh Chen

IPC: H10N50/80 ,  H10B61/00 ,  H10N50/01 ,  H10N50/20 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of forming a magnetic tunneling junction (MTJ) on a MRAM region of a substrate, forming a first inter-metal dielectric (IMD) layer around the MTJ, forming a patterned mask on a logic region of the substrate, performing a nitridation process to transform part of the first IMD layer to a nitride layer, forming a first metal interconnection on the logic region, forming a stop layer on the first IMD layer, forming a second IMD layer on the stop layer, and forming a second metal intercom in the second IMD layer to connect to the MTJ.

公开(公告)号：US20250035718A1

公开(公告)日：2025-01-30

申请号：US18915389

申请日：2024-10-15

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Chen -Yi Weng ,  Che-Wei Chang ,  Si-Han Tsai ,  Ching-Hua Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang

IPC: G01R33/09 ,  G11C11/02 ,  H10B61/00 ,  H10N50/01 ,  H10N50/10 ,  H10N50/80 ,  H10N50/85

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, in which the MTJ includes a pinned layer on the substrate, a reference layer on the pinned layer, a barrier layer on the reference layer, and a free layer on the barrier layer. Preferably, the free layer and the barrier layer have same width and the barrier layer and the reference layer have different widths.

公开(公告)号：US20250015023A1

公开(公告)日：2025-01-09

申请号：US18229640

申请日：2023-08-02

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chiu-Jung Chiu ,  Chung-Hsing Kuo ,  Chun-Ting Yeh ,  Chuan-Lan Lin ,  Yu-Ping Wang ,  Yu-Chun Chen

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/528 ,  H01L23/532

Abstract: The invention provides a semiconductor structure, which comprises a plurality of metal circuit layers stacked with each other, the multi-layer metal circuit layer comprises an aluminum circuit layer which is located at the position closest to a surface among the plurality of circuit layers, the material of the aluminum circuit layer is made of aluminum, and the aluminum circuit layer comprises a concave portion.

公开(公告)号：US20240387418A1

公开(公告)日：2024-11-21

申请号：US18209486

申请日：2023-06-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Yu-Ping Wang ,  I-Ming Tseng ,  Yi-An Shih ,  Chung-Sung Chiang ,  Chiu-Jung Chiu

IPC: H01L23/00 ,  H01L21/768 ,  H01L23/522 ,  H01L25/065

Abstract: A semiconductor device includes a bottom wafer, a top wafer bonded to the bottom wafer, a first dielectric layer, a second dielectric layer, a deep via conductor structure, and a connection pad. The top wafer includes a first interconnection structure. The first dielectric layer is disposed on the top wafer. The second dielectric layer is disposed on the first dielectric layer. The deep via conductor structure penetrates through the second dielectric layer and the first dielectric layer and is connected with the first interconnection structure. The connection pad is disposed on the second dielectric layer and the deep via conductor structure. A first portion of the second dielectric layer is sandwiched between the connection pad and the first dielectric layer. A second portion of the second dielectric layer is connected with the first portion, and a thickness of the second portion is less than a thickness of the first portion.

公开(公告)号：US20240371758A1

公开(公告)日：2024-11-07

申请号：US18203655

申请日：2023-05-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Chun Chen ,  Yu-Ping Wang ,  I-Ming Tseng ,  Yi-An Shih ,  Chung-Sung Chiang ,  Chiu-Jung Chiu

IPC: H01L23/528 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H01L25/065

Abstract: A method for fabricating a semiconductor device includes the steps of first bonding a top wafer to a bottom wafer, in which the top wafer has a first metal interconnection including a first barrier layer exposing from a bottom surface of the top wafer. Next, a dielectric layer is formed on the bottom surface of the top wafer and then a second metal interconnection is formed in the dielectric layer and connected to the first metal interconnection, in which the second metal interconnection includes a second barrier layer and the first barrier layer and the second barrier layer include a H-shape altogether.

公开(公告)号：US12063792B2

公开(公告)日：2024-08-13

申请号：US18207654

申请日：2023-06-08

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Hui-Lin Wang ,  Po-Kai Hsu ,  Jing-Yin Jhang ,  Yu-Ping Wang ,  Hung-Yueh Chen ,  Wei Chen

IPC: H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

CPC classification number: H10B61/22 ,  H10N50/01 ,  H10N50/80 ,  H10N50/85

Abstract: A method for fabricating a semiconductor device includes the steps of: forming a magnetic tunneling junction (MTJ) on a substrate; forming a first inter-metal dielectric (IMD) layer around the MTJ; forming a first metal interconnection adjacent to the MTJ; forming a stop layer on the first IMD layer; removing the stop layer to form an opening; and forming a channel layer in the opening to electrically connect the MTJ and the first metal interconnection.