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    POST-MANUFACTURE LATCH TIMING CONTROL BLOCKS IN PIPELINED PROCESSORS
    151.
    发明公开
    POST-MANUFACTURE LATCH TIMING CONTROL BLOCKS IN PIPELINED PROCESSORS 审中-公开

    公开(公告)号：US20230341888A1

    公开(公告)日：2023-10-26

    申请号：US17726171

    申请日：2022-04-21

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Vivek Raj ,  Sunil Kumar ,  Shivraj G. Dharne ,  Mahbub Rashed

    IPC: G06F1/10 ,  G06F15/78

    CPC classification number: G06F1/10 ,  G06F15/7839

    Abstract: An apparatus includes a series of pipeline stages that have logic components connected to supply output data to latch components, timing correction blocks connected to the latch components, and a memory component connected to supply a correction pattern to the timing correction blocks. The timing correction blocks have a buffer connected to a multiplexor. The correction pattern controls whether the multiplexor receives an adjusted clock signal through the buffer to control whether the timing correction blocks supply an unadjusted clock signal or the adjusted clock signal to the latch components.

    WAVEGUIDES AND EDGE COUPLERS WITH MULTIPLE-THICKNESS WAVEGUIDE CORES
    152.
    发明公开
    WAVEGUIDES AND EDGE COUPLERS WITH MULTIPLE-THICKNESS WAVEGUIDE CORES 审中-公开

    公开(公告)号：US20230341637A1

    公开(公告)日：2023-10-26

    申请号：US17729244

    申请日：2022-04-26

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Yusheng Bian

    IPC: G02B6/42

    CPC classification number: G02B6/4206 ,  G02B6/42

    Abstract: Photonics structures for a waveguide or an edge coupler and methods of fabricating a photonics structure for a waveguide or an edge coupler. The photonics structure includes a waveguide core having a first section, a second section longitudinally adjacent to the first section, first segments projecting in a vertical direction from the first section, and second segments projecting in the vertical direction from the second section. The first section of the waveguide core has a first thickness, and the second section of the waveguide core has a second thickness that is greater than the first thickness.

    DEEP TRENCH ISOLATION STRUCTURES WITH A SUBSTRATE CONNECTION
    153.
    发明公开
    DEEP TRENCH ISOLATION STRUCTURES WITH A SUBSTRATE CONNECTION 审中-公开

    公开(公告)号：US20230335583A1

    公开(公告)日：2023-10-19

    申请号：US17723665

    申请日：2022-04-19

    Applicant: GlobalFoundries Singapore Pte. Ltd.

    Inventor： Jianbo Zhou ,  Shiang Yang Ong ,  Namchil Mun ,  Hung Chang Liao ,  Zhongxiu Yang

    IPC: H01L21/762 ,  H01L29/06

    CPC classification number: H01L29/0649 ,  H01L21/762

    Abstract: Semiconductor structures including a deep trench isolation structure and methods of forming a semiconductor structure including a deep trench isolation structure. The semiconductor structure includes a semiconductor substrate having a device region, and a deep trench isolation structure in the semiconductor substrate. The deep trench isolation structure further includes a first portion, a second portion adjacent to the first portion, and a conductor layer in the first portion and the second portion. The conductor layer in the first portion of the deep trench isolation structure surrounds the device region. The conductor layer in the second portion of the deep trench isolation structure defines an electrical connection to the semiconductor substrate.

    FIELD EFFECT TRANSISTOR WITH BURIED FLUID-BASED GATE AND METHOD
    157.
    发明公开
    FIELD EFFECT TRANSISTOR WITH BURIED FLUID-BASED GATE AND METHOD 审中-公开

    公开(公告)号：US20230324332A1

    公开(公告)日：2023-10-12

    申请号：US17715282

    申请日：2022-04-07

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Mark D. Levy ,  Siva P. Adusumilli ,  Aaron L. Vallett

    IPC: G01N27/414

    CPC classification number: G01N27/4148 ,  G01N27/4145

    Abstract: Disclosed is a semiconductor structure including a device (e.g., a field effect transistor (FET), a biosensor FET (bioFET) or an ion-sensitive FET (ISFET)) with a fluid-based gate. The structure includes a substrate, an intermediate layer on the substrate, and a semiconductor layer on the intermediate layer. The device includes, within the semiconductor layer, a source region, a drain region, and a channel region between the source and drain regions. The structure includes, for the fluid-base gate, a cavity within the intermediate layer below the channel region and lined with a dielectric liner. Optionally, the exposed surface of the dielectric liner within the cavity is functionalized. Additional dielectric layers are stacked on the semiconductor layer and at least one port extends essentially vertically through the dielectric layers, the semiconductor layer and the dielectric liner to the cavity so as to allow fluid for the fluid-based gate to flow into the cavity.

    Monolithic integration of diverse device types with shared electrical isolation
    159.
    发明授权
    Monolithic integration of diverse device types with shared electrical isolation 有权

    公开(公告)号：US11784189B2

    公开(公告)日：2023-10-10

    申请号：US17407680

    申请日：2021-08-20

    Applicant: GLOBALFOUNDRIES U.S. Inc.

    Inventor： Francois Hebert ,  Handoko Linewih

    IPC: H01L27/12 ,  H01L21/84 ,  H01L27/085 ,  H01L29/872

    CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L27/085 ,  H01L29/872

    Abstract: Structures including III-V compound semiconductor-based devices and silicon-based devices integrated on a semiconductor substrate and methods of forming such structures. The structure includes a substrate having a device layer, a handle substrate, and a buried insulator layer between the handle substrate and the device layer. The structure includes a first semiconductor layer on the device layer in a first device region, and a second semiconductor layer on the device layer in a second device region. The first semiconductor layer contains a III-V compound semiconductor material, and the second semiconductor layer contains silicon. A first device structure includes a gate structure on the first semiconductor layer, and a second device structure includes a doped region in the second semiconductor layer. The doped region and the second semiconductor layer define a p-n junction.

    Wavelength-division-multiplexing filter stages with segmented wavelength splitters
    160.
    发明授权
    Wavelength-division-multiplexing filter stages with segmented wavelength splitters 有权

    公开(公告)号：US11782208B1

    公开(公告)日：2023-10-10

    申请号：US17858549

    申请日：2022-07-06

    Applicant: GlobalFoundries U.S. Inc.

    Inventor： Yusheng Bian

    IPC: G02B6/12 ,  G02B6/13 ,  G02B6/293

    CPC classification number: G02B6/12007 ,  G02B6/13 ,  G02B6/2938 ,  G02B6/29352 ,  G02B6/29325 ,  G02B2006/12061 ,  G02B2006/12097 ,  G02B2006/12164

    Abstract: Structures for a wavelength splitter used in a wavelength-division-multiplexing filter stage and methods of forming same. The structure comprises a first waveguide core including a first section, a second section, and a phase delay line between the first section and the second section. The phase delay line of the first waveguide core includes a delay section and a plurality of segments longitudinally arranged in the delay section. The structure further comprises a second waveguide core including a first section, a second section, and a phase delay line between the first section and the second section. The first section of the second waveguide core is positioned adjacent to the first section of the first waveguide core to define a first directional coupler, and the second section of the second waveguide core is positioned adjacent to the second section of the first waveguide core to define a second directional coupler.

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