Apparatus and Methods for Analysis of Gene Mutation

    公开(公告)号:US20240117442A1

    公开(公告)日:2024-04-11

    申请号:US18490116

    申请日:2023-10-19

    CPC classification number: C12Q1/6886 C12Q2600/156 C12Q2600/166

    Abstract: Methods and apparatuses are disclosed for detecting a presence of a mismatched pair in an oligonucleotide duplex that is attached to a solid substrate using an atomic force microscope. In particular, methods and apparatuses of the invention allow qualitative and quantitative analysis of the presence of a mismatched pair in a sample of oligonucleotide duplex using an atomic force microscope comprising an AFM cantilever that includes a DNA mismatch repair protein. Methods and apparatuses of the invention allow detection of gene mutation without a need for amplification, labeling, or modification of the sample. Such apparatuses and methods can be used in a wide variety of clinical diagnostic applications including detection and/or analysis of biomarkers related to, but not limited to, cancer, trauma, sepsis, aseptic inflammation, myocardial infarction, stroke, transplantation, diabetes, sickle cell disease, as well as other clinical conditions.

    Ternary logic circuit device
    160.
    发明授权

    公开(公告)号:US11868740B2

    公开(公告)日:2024-01-09

    申请号:US17489629

    申请日:2021-09-29

    CPC classification number: G06F7/502 H03K19/173 H03K19/094

    Abstract: A circuit includes a first full adder, a second full adder, a first half adder, a third full adder configured to receive a sum output signal of the first full adder, a sum output signal of the second full adder, and a sum output signal of the first half adder, a fourth full adder configured to receive a carry output signal of the first full adder, a carry output signal of the second full adder, and a carry output signal of the first half adder, a second half adder configured to receive a carry output signal of the third full adder and a sum output signal of the fourth full adder, and a third half adder configured to receive a carry output signal of the second half adder and a carry output signal of the fourth full adder.

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