公开(公告)号：US08902025B2

公开(公告)日：2014-12-02

申请号：US13736913

申请日：2013-01-08

Applicant: STMicroelectronics SA

Inventor： Sébastien Pruvost ,  Frédéric Gianessello

IPC: H01P5/00 ,  H01P3/06 ,  H01P3/00

CPC classification number: H01P3/003 ,  H01P3/006 ,  H01P3/082

Abstract: An embodiment relates to a coplanar waveguide electronic device comprising a substrate whereon is mounted a signal ribbon and at least a ground plane. The signal ribbon comprises a plurality of signal lines of a same level of metallization electrically connected together, and the ground plane is made of an electrically conducting material and comprises a plurality of holes.

Abstract translation: 一个实施例涉及一种共面波导电子器件，其包括其上安装有信号带和至少一个接地平面的衬底。 信号带包括电连接在一起的相同级别的金属化的多条信号线，并且接地平面由导电材料制成并且包括多个孔。

公开(公告)号：US20140347906A1

公开(公告)日：2014-11-27

申请号：US14280833

申请日：2014-05-19

Applicant: STMicroelectronics SA

Inventor： Olivier Menut ,  David Turgis ,  Lorenzo Ciampolini

IPC: G11C15/04

CPC classification number: G11C15/046 ,  G11C15/04

Abstract: A ternary content-addressable cell is configured to compare an input binary data item present on an input terminal with two reference binary data items, and to output a match signal on a match line. The cell includes: a first storage circuit (storing a potential representing the first reference binary data item) and a second storage cell (storing a potential representing the second reference binary data item). A comparison circuit is connected to the first and second storage circuits and to the input terminal SL. A comparison node presents a potential representing the comparison of the input binary data item with the first and second reference data items. The comparison node is connected to an output stage, and the output stage is connected to the match line. The signal on the match line is based on the potential of the comparison node.

Abstract translation: 三元内容寻址单元被配置为将输入端上存在的输入二进制数据项与两个参考二进制数据项进行比较，并在匹配线上输出匹配信号。 小区包括：第一存储电路（存储表示第一参考二进制数据项的电位）和第二存储单元（存储表示第二参考二进制数据项的电位）。 比较电路连接到第一和第二存储电路和输入端子SL。 比较节点呈现表示输入二进制数据项与第一和第二参考数据项的比较的潜力。 比较节点连接到输出级，输出级连接到匹配线。 匹配线上的信号基于比较节点的电位。

公开(公告)号：US20140341499A1

公开(公告)日：2014-11-20

申请号：US14271723

申请日：2014-05-07

Applicant: STMICROELECTRONICS SA

Inventor： Jean-Robert MANOUVRIER

IPC: G02F1/225 ,  G02F1/025 ,  H01L33/00 ,  G02F1/015

CPC classification number: G02F1/2257 ,  G02F1/015 ,  G02F1/025 ,  G02F2001/212 ,  G02F2203/20 ,  H01L33/0012

Abstract: A semiconductor electro-optical phase shifter comprises a central zone (I1, I2) having a minimum doping level; first and second lateral zones (N+, P+) flanking the central zone along a first axis, respectively N and P-doped, so as to form a P-I-N junction between the first and second lateral zones. The central zone comprises first and second optical action zones (I1, I2) separated along the first axis. The second lateral zone is doped discontinuously along a second axis perpendicular to the first axis. Two electrical control terminals (A, C) are provided, one in contact with the first lateral zone, and the other in contact with doped portions of the second lateral zone.

Abstract translation: 半导体电光移相器包括具有最小掺杂水平的中心区（I1，I2）; 第一和第二侧向区域（N +，P +）分别沿着第一轴线分别位于中心区域N和P掺杂，以便在第一和第二侧向区域之间形成P-I-N结。 中心区域包括沿着第一轴线分离的第一和第二光学作用区域（I1，I2）。 第二横向区域沿着垂直于第一轴线的第二轴线不连续地掺杂。 设置两个电气控制端子（A，C），一个与第一侧向区域接触，另一个与第二侧向区域的掺杂部分接触。

公开(公告)号：US20140335663A1

公开(公告)日：2014-11-13

申请号：US14177614

申请日：2014-02-11

Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT ,  STMICROELECTRONICS SA ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Heimanu NIEBOJEWSKI ,  Yves Morand ,  Maud Vinet

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/6656 ,  H01L21/84 ,  H01L27/1203 ,  H01L29/66636 ,  H01L29/66772 ,  H01L29/78603

Abstract: A method for manufacturing a transistor includes forming a stack of semiconductor on insulator type layers including at least one substrate, surmounted by a first insulating layer and an active layer to form a channel for the transistor; forming a gate stack on the active layer; producing a source and a drain including forming, on either side of the gate stack, cavities by at least one step of etching the active layer, the first insulating layer, and part of the substrate selectively to the gate stack to remove the active layer, the first insulating layer, and a portion of the substrate outside regions situated below the gate stack; forming a second insulating layer on the bared surfaces of the substrate, to form a continuous insulating layer with the first insulating layer; baring of the lateral ends of the channel; and the filling of the cavities by epitaxy.

Abstract translation: 一种制造晶体管的方法，包括：形成绝缘体上半导体层的叠层，其包括至少一个衬底，其被第一绝缘层和有源层所覆盖以形成晶体管的沟道; 在有源层上形成栅叠层; 产生源极和漏极，包括在栅叠层的任一侧通过至少一个步骤，至少一个步骤，将有源层，第一绝缘层和衬底的一部分选择性地栅极堆叠以形成去除有源层， 所述第一绝缘层和位于所述栅叠层下方的所述衬底外部区域的一部分; 在所述基板的裸露表面上形成第二绝缘层，以形成具有所述第一绝缘层的连续绝缘层; 通道的横向端部露出; 并通过外延填充空腔。

公开(公告)号：US20140287705A1

公开(公告)日：2014-09-25

申请号：US14219716

申请日：2014-03-19

Applicant: STMICROELECTRONICS (GRENOBLE 2) SAS ,  STMICROELECTRONICS SA

Inventor： Vincent Heinrich ,  Bruno Paille

IPC: H03D3/06

CPC classification number: H03D3/06 ,  H04L27/144 ,  H04L27/16

Abstract: A method and corresponding device for processing a frequency-modulated analog signal are disclosed. The signal includes a number of symbols belonging to a set of M symbols respectively associated with at least one frequency of a set of M frequencies. The method includes a phase of reading each symbol of the signal that includes a sampling of a signal portion corresponding to the duration of a symbol and delivering N samples (M being less than N). M individual discrete Fourier transform processing operations are performed on the N samples. Each individual processing operation is associated with each of the frequencies. The M individual processing operations deliver M processing results. The value of the symbol can be determined from the M processing results.

Abstract translation: 公开了一种用于处理调频模拟信号的方法和相应装置。 信号包括属于一组M个符号的符号的数目，分别与一组M个频率的至少一个频率相关联。 该方法包括读取信号的每个符号的相位，其包括对应于符号的持续时间的信号部分的采样，并且递送N个采样（M小于N）。 对N个样本执行M个离散傅立叶变换处理操作。 每个单独的处理操作与每个频率相关联。 M个人处理操作提供M个处理结果。 可以从M处理结果确定符号的值。

公开(公告)号：US20140232575A1

公开(公告)日：2014-08-21

申请号：US14179993

申请日：2014-02-13

Applicant: STMICROELECTRONICS SA

Inventor： Nicolas Le Dortz ,  Thierry Simon ,  Pascal Urard ,  Caroline Lelandais-Perrault

IPC: H03M1/06

CPC classification number: H03M1/0624 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1215 ,  H03M1/1225

Abstract: According to one mode of implementation, a method includes an estimation including on the one hand a correlation processing involving at least one part of the sampled signal, at least one part of at least one first signal gleaned from a derived signal representative of a temporal derivative of the sampled signal and at least one part of N partial filtered signals respectively representative of N weighted differences between N pairs of bracketing versions flanking the sampled signal, N being greater than or equal to 1. On the other hand, the estimation includes a matrix processing on the results of this correlation processing. Correction processing of the M−1 trains involves respectively M−1 second signals gleaned from the derived signal and the suite of M−1 shift coefficients.

Abstract translation: 根据一种实施方式，一种方法包括估计，其一方面包括涉及采样信号的至少一部分的相关处理，从代表时间导数的导出信号中收集的至少一个第一信号的至少一部分 的采样信号和N个部分滤波信号的至少一部分，分别代表在采样信号侧翼的N对包围版本之间的N个加权差，N大于或等于1.另一方面，估计包括矩阵 对该相关处理的结果进行处理。 M-1列车的校正处理涉及从派生信号和一组M-1移位系数收集的M-1个第二信号。

公开(公告)号：US20140231916A1

公开(公告)日：2014-08-21

申请号：US14156559

申请日：2014-01-16

Applicant: STMicroelectronics SA ,  Commissariat a I'energie atomique et aux energies alternatives

Inventor： Bastien Giraud ,  Jean-Philippe Noel ,  Maud Vinet

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/78 ,  H01L29/42392 ,  H01L29/66575 ,  H01L29/785 ,  H01L29/7855 ,  H01L29/7856 ,  H01L29/78696

Abstract: An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.

Abstract translation: 集成电路包括硅衬底，衬底上方的接地平面，接地平面上方的掩埋绝缘体层，掩埋绝缘体层上方的硅层，并由掩埋绝缘体层与接地层分离，以及FDSOI晶体管。 晶体管具有适于在硅层中形成的沟道，硅层中和/或硅层上的源极和漏极，以及覆盖沟道的上表面的栅极，并且具有覆盖沟道的侧面的侧面部分，以及 在地面以上。 横向部分和接地面之间的距离不大于接地平面和硅层之间的掩埋绝缘体层的厚度的三纳米至少五倍。 接地层由掩埋绝缘体层与栅极分离。

公开(公告)号：US20140176228A1

公开(公告)日：2014-06-26

申请号：US14134081

申请日：2013-12-19

Applicant: Commissariat à l'énergie atomique et aux énergies alternatives ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics SA

Inventor： Bastien Giraud ,  Fady Abouzeid ,  Sylvain Clerc ,  Jean-Philippe Noel ,  Yvain Thonnart

IPC: G05F3/02

CPC classification number: G05F3/02 ,  H01L21/84 ,  H01L27/11807 ,  H01L27/1203 ,  H01L29/78648 ,  H03K19/1774

Abstract: The invention relates to an integrated circuit comprising: a first semiconductor well (60); a plurality of standard cells (66), each standard cell comprising a first field-effect transistor in FDSOI technology comprising a first semiconductor ground plane located immediately on the first well; and a clock tree cell (30) contiguous with the standard cells, the clock tree cell comprising a second field-effect transistor in FDSOI technology, which transistor comprises a second semiconductor ground plane located immediately on the first well (60), so as to form a p-n junction with this first well. The integrated circuit comprises an electrical power supply network (51) able to apply separate electrical biases directly to the first and second ground planes.

Abstract translation: 本发明涉及一种集成电路，包括：第一半导体阱（60）; 多个标准单元（66），每个标准单元包括FDSOI技术中的第一场效应晶体管，其包括位于第一阱上的第一半导体接地平面; 以及与所述标准单元相邻的时钟树单元（30），所述时钟树单元包括FDSOI技术中的第二场效应晶体管，所述晶体管包括位于所述第一阱（60）上的第二半导体接地平面，以便 与第一口井形成一个pn结。 集成电路包括能够将分离的电偏压直接施加到第一和第二接地层的电力供应网络（51）。

公开(公告)号：US20140167527A1

公开(公告)日：2014-06-19

申请号：US14062455

申请日：2013-10-24

Applicant: STMicroelectronics SA

Inventor： Severin Trochut ,  Emilie Rigal ,  Fabrice Blisson ,  Frederic Hasbani ,  Nicolas Seller

IPC: H03K17/687

CPC classification number: H03K17/6871 ,  G06F1/3287 ,  H03K17/22 ,  Y02D10/171 ,  Y10T307/76

Abstract: A chain of switches is connected between a first power supply line coupled to a first voltage and a second power supply line coupled to the sector. These switches are controllable by a control signal. The control signal is propagated from a first end of the first chain towards a second end of the first chain without control of the switches during this first propagation. The control signal is then propagated in the reverse direction from the second end towards the first end with a control of the switches during this second propagation starting from a group of at least one switch situated at the second end. There is a detection of the arrival of the control signal at the first end of the chain at the end of its propagation in the reverse direction.

Abstract translation: 一连串的开关连接在耦合到第一电压的第一电源线和耦合到扇区的第二电源线之间。 这些开关由控制信号控制。 控制信号从第一链的第一端传播到第一链的第二端，而在该第一次传播期间不控制开关。 然后，控制信号从第二端朝向第一端的相反方向传播，在第二次传播期间通过位于第二端的一组至少一个开关的一组开关进行控制。 在反向传播结束时，检测到链的第一端处的控制信号的到达。

公开(公告)号：US20140167167A1

公开(公告)日：2014-06-19

申请号：US14096509

申请日：2013-12-04

Applicant: STMICROELECTRONICS SA

Inventor： Frederic HASBANI ,  Eric Remond

IPC: H01L27/12 ,  H01L21/84

CPC classification number: H01L27/1203 ,  H01L21/84 ,  H01L29/78648

Abstract: An integrated cell may include an nMOS transistor, and an pMOS transistor. The cell may be produced in fully depleted silicon-on-insulator technology, and it is possible for the substrates of the transistors of the cell to be biased with the same adjustable biasing voltage.

Abstract translation: 集成单元可以包括nMOS晶体管和pMOS晶体管。 电池可以在完全耗尽的绝缘体上的技术中制造，并且可以以相同的可调偏置电压来偏置电池的晶体管的衬底。