公开(公告)号：US20200166709A1

公开(公告)日：2020-05-28

申请号：US16199811

申请日：2018-11-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob

IPC: G02B6/34

Abstract: Structures for a waveguide and methods of fabricating a structure for a waveguide. A grating coupler is formed that has an arrangement of grating structures. A conformal layer is arranged over the plurality of grating structures. The conformal layer is composed of a tunable material having a refractive index that changes with an applied voltage.

公开(公告)号：US10665281B1

公开(公告)日：2020-05-26

申请号：US16286942

申请日：2019-02-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Amogh Agrawal ,  Bipul C. Paul

IPC: G11C11/16 ,  H01L27/22

Abstract: A device is disclosed including a first resistive storage element, a first access transistor having a first terminal coupled to the first resistive storage element at a first node, a second resistive storage element, a second access transistor having a first terminal coupled to the second resistive storage element at a second node, and a write assist transistor having a first terminal coupled to the first node and a second terminal coupled to the second node.

公开(公告)号：US10649245B1

公开(公告)日：2020-05-12

申请号：US16298446

申请日：2019-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Abu Thomas

IPC: G02F1/035 ,  G02F1/025 ,  G02F1/015

Abstract: Structures for an electro-optic modulator and methods of fabricating a structure for an electro-optic modulator. The electro-optic modulator is arranged over a portion of a first waveguide core. The electro-optic modulator may include an electrode, an active layer, a second waveguide core, and a dielectric layer that is arranged between the active layer and the second waveguide core. The active layer is composed of a material having a refractive index that is a function of a bias voltage applied between the electrode and the first waveguide core.

公开(公告)号：US10585219B2

公开(公告)日：2020-03-10

申请号：US16000249

申请日：2018-06-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Yusheng Bian

IPC: G02B6/34 ,  G02B5/18 ,  G02B6/42 ,  G02B6/12 ,  G02B6/293 ,  G02B6/124

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers with multiple configurations and methods of manufacture. A grating coupler structure includes: a polysilicon material with a first grating coupling pattern; a SiN material with second grating coupling pattern; a dielectric material covering the polysilicon material and the SiN material; and a back end of line (BEOL) multilayer stack over the dielectric material.

公开(公告)号：US10444433B1

公开(公告)日：2019-10-15

申请号：US16170262

申请日：2018-10-25

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Abu Thomas ,  Ajey Poovannummoottil Jacob ,  Kenneth J. Giewont ,  Karen Nummy ,  Andreas Stricker ,  Bo Peng

IPC: G02B6/122 ,  G02B6/136 ,  G02B6/12

Abstract: Structures that include a waveguide and methods of fabricating a structure that includes a waveguide. A tapered feature composed of a dielectric material is arranged over the waveguide. The tapered feature includes a sidewall that is angled relative to a longitudinal axis of the waveguide.

公开(公告)号：US10429582B1

公开(公告)日：2019-10-01

申请号：US15968997

申请日：2018-05-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yusheng Bian ,  Ajey Poovannummoottil Jacob ,  Steven M. Shank

IPC: G02B6/26 ,  G02B6/122 ,  G02B6/136 ,  G02B6/125 ,  G02B6/124 ,  G02B6/12

Abstract: Waveguide-to-waveguide couplers, systems that include waveguide-to-waveguide couplers, and methods of fabricating waveguide-to-waveguide couplers. A first waveguide is coupled to a first waveguide taper, and a second waveguide is coupled to a second waveguide taper. The first waveguide and the first waveguide taper are comprised of silicon, and the second waveguide and the second waveguide taper are comprised of silicon nitride. The second waveguide and the second waveguide taper are arranged in a vertical direction over the first waveguide and the first waveguide taper.

公开(公告)号：US20190259810A1

公开(公告)日：2019-08-22

申请号：US15898562

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jaiswal Akhilesh

IPC: H01L27/22 ,  G11C11/16 ,  H01L43/02 ,  H01L43/12 ,  H01L43/08

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have complement magnetizations.

公开(公告)号：US20190259809A1

公开(公告)日：2019-08-22

申请号：US15898555

申请日：2018-02-17

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Ajey Poovannummoottil Jacob ,  Jaiswal Akhilesh

IPC: H01L27/22 ,  H01L43/04 ,  H01L43/14 ,  G11C11/16 ,  H01L43/06 ,  G11C11/18

Abstract: Integrated circuits and methods for fabricating integrated circuits are provided herein. The integrated circuit includes a plurality of MRAM structures. The integrated circuit further includes a first lower MTJ stack with the first lower MTJ stack including a first lower free layer. The integrated circuit further includes a spin orbit torque coupling layer overlying the first lower MTJ stack. The integrated circuit further includes a first upper MTJ stack overlying the spin orbit torque coupling layer and the first lower MTJ stack with the first upper MTJ stack including a first upper free layer. The switching energy barrier for each of the first lower free layer and the first upper free layer is reduced in the presence of an electrical voltage passing through each of the MTJ stacks. The first lower free layer and said first upper free layer are configured to have magnetizations independent of each other.

公开(公告)号：US10241269B1

公开(公告)日：2019-03-26

申请号：US15974252

申请日：2018-05-08

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ajey Poovannummoottil Jacob ,  Yusheng Bian

IPC: G02B6/124 ,  G02B6/12

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to grating couplers with multiple configurations and methods of manufacture. A structure includes: a grating coupler having a sawtooth configuration provided over a semiconductor slab; and a back end of line (BEOL) stack over the sawtooth configuration of the grating coupler.

公开(公告)号：US10186577B2

公开(公告)日：2019-01-22

申请号：US14477096

申请日：2014-09-04

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven Bentley ,  Richard A. Farrell ,  Gerard Schmid ,  Ajey Poovannummoottil Jacob

IPC: H01L29/06 ,  H01L29/78 ,  H01L21/3105 ,  H01L21/308 ,  B82Y10/00 ,  B82Y40/00 ,  H01L29/66 ,  H01L29/775 ,  H01L21/311

Abstract: A method includes forming a first directed self-assembly material above a substrate. The substrate is patterned using the first directed self-assembly material to define at least one fin in the semiconductor substrate. A second directed self-assembly material is formed above the at least one fin to expose a top surface of the at least one fin. A substantially vertical nanowire is formed on the top surface of the at least one fin. At least a first dimension of the vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material and a second dimension of the vertical nanowire is defined by an intrinsic pitch of the second directed self-assembly material.