公开(公告)号：US10886386B2

公开(公告)日：2021-01-05

申请号：US15806160

申请日：2017-11-07

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu

IPC: H01L21/82 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8234

Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.

公开(公告)号：US10861984B2

公开(公告)日：2020-12-08

申请号：US16564860

申请日：2019-09-09

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/84 ,  H01H59/00 ,  H01H1/00 ,  B82B3/00 ,  H01H49/00 ,  H01L21/02 ,  H01L21/306 ,  H01H50/00

Abstract: An integrated transistor in the form of a nanoscale electromechanical switch eliminates CMOS current leakage and increases switching speed. The nanoscale electromechanical switch features a semiconducting cantilever that extends from a portion of the substrate into a cavity. The cantilever flexes in response to a voltage applied to the transistor gate thus forming a conducting channel underneath the gate. When the device is off, the cantilever returns to its resting position. Such motion of the cantilever breaks the circuit, restoring a void underneath the gate that blocks current flow, thus solving the problem of leakage. Fabrication of the nano-electromechanical switch is compatible with existing CMOS transistor fabrication processes. By doping the cantilever and using a back bias and a metallic cantilever tip, sensitivity of the switch can be further improved. A footprint of the nano-electromechanical switch can be as small as 0.1×0.1 μm2.

公开(公告)号：US10580771B2

公开(公告)日：2020-03-03

申请号：US16049685

申请日：2018-07-30

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  Prasanna Khare ,  Nicolas Loubet

IPC: H01L21/84 ,  H01L29/66 ,  H01L29/78 ,  H01L21/8238 ,  H01L27/088 ,  H01L29/08 ,  H01L21/265 ,  H01L29/417 ,  H01L21/225 ,  H01L21/8234

Abstract: A multi-fin FINFET device may include a substrate and a plurality of semiconductor fins extending upwardly from the substrate and being spaced apart along the substrate. Each semiconductor fin may have opposing first and second ends and a medial portion therebetween, and outermost fins of the plurality of semiconductor fins may comprise an epitaxial growth barrier on outside surfaces thereof. The FINFET may further include at least one gate overlying the medial portions of the semiconductor fins, a plurality of raised epitaxial semiconductor source regions between the semiconductor fins adjacent the first ends thereof, and a plurality of raised epitaxial semiconductor drain regions between the semiconductor fins adjacent the second ends thereof.

公开(公告)号：US10324254B2

公开(公告)日：2019-06-18

申请号：US15962633

申请日：2018-04-25

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: G02B6/10 ,  G02B6/136 ,  G02B6/122 ,  C30B23/04 ,  C30B25/04 ,  C30B29/06 ,  G02B6/13 ,  G02B6/12 ,  G02B6/032

Abstract: A strip of sacrificial semiconductor material is formed on top of a non-sacrificial semiconductor material substrate layer. A conformal layer of the non-sacrificial semiconductor material is epitaxially grown to cover the substrate layer and the strip of sacrificial semiconductor material. An etch is performed to selectively remove the strip of sacrificial semiconductor material and leave a hollow channel surrounded by the conformal layer and the substrate layer. Using an anneal, the conformal layer and the substrate layer are reflowed to produce an optical waveguide structure including the hollow channel.

公开(公告)号：US10084080B2

公开(公告)日：2018-09-25

申请号：US14675298

申请日：2015-03-31

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu ,  John H. Zhang

IPC: H01L29/66 ,  H01L21/8238 ,  H01L21/336 ,  H01L29/78 ,  H01L29/165 ,  H01L29/267 ,  H01L29/739 ,  H01L27/092 ,  H01L29/16 ,  H01L21/8234 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L29/7827 ,  H01L21/823487 ,  H01L21/823885 ,  H01L27/092 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/267 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66356 ,  H01L29/66666 ,  H01L29/7391 ,  H01L29/785

Abstract: A tunneling transistor is implemented in silicon, using a FinFET device architecture. The tunneling FinFET has a non-planar, vertical, structure that extends out from the surface of a doped drain formed in a silicon substrate. The vertical structure includes a lightly doped fin defined by a subtractive etch process, and a heavily-doped source formed on top of the fin by epitaxial growth. The drain and channel have similar polarity, which is opposite that of the source. A gate abuts the channel region, capacitively controlling current flow through the channel from opposite sides. Source, drain, and gate terminals are all electrically accessible via front side contacts formed after completion of the device. Fabrication of the tunneling FinFET is compatible with conventional CMOS manufacturing processes, including replacement metal gate and self-aligned contact processes. Low-power operation allows the tunneling FinFET to provide a high current density compared with conventional planar devices.

公开(公告)号：US20180076306A1

公开(公告)日：2018-03-15

申请号：US15806160

申请日：2017-11-07

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/785

Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.

公开(公告)号：US09899253B2

公开(公告)日：2018-02-20

申请号：US15262034

申请日：2016-09-12

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  STMICROELECTRONICS, INC.

Inventor： Bruce Doris ,  Hong He ,  Qing Liu

IPC: H01L21/762 ,  H01L29/78 ,  H01L29/06 ,  H01L29/08 ,  H01L29/165 ,  H01L21/02 ,  H01L21/225 ,  H01L27/12 ,  H01L29/66 ,  H01L29/10

CPC classification number: H01L21/76283 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/2254 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/785 ,  H01L2029/7858

Abstract: A method of making a structurally stable SiGe-on-insulator FinFET employs a silicon nitride liner to prevent de-stabilizing oxidation at the base of a SiGe fin. The silicon nitride liner blocks access of oxygen to the lower corners of the fin to facilitate fabrication of a high-concentration SiGe fin. The silicon nitride liner is effective as an oxide barrier even if its thickness is less than about 5 nm. Use of the SiN liner provides structural stability for fins that have higher germanium content, in the range of 25-55% germanium concentration.

公开(公告)号：US09865710B2

公开(公告)日：2018-01-09

申请号：US14843221

申请日：2015-09-02

Applicant: STMICROELECTRONICS, INC.

Inventor： Qing Liu

IPC: H01L21/306 ,  H01L21/78 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66818 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/785

Abstract: A dual width SOI FinFET is disclosed in which different portions of a strained fin have different widths. A method of fabrication of such a dual width FinFET entails laterally recessing the strained fin in the source and drain regions using a wet chemical etching process so as to maintain a high degree of strain in the fin while trimming the widths of fin portions in the source and drain regions to less than 5 nm. The resulting FinFET features a wide portion of the fin in the channel region underneath the gate, and a narrower portion of the fin in the source and drain regions. An advantage of the narrower fin is that it can be more easily doped during the growth of the epitaxial raised source and drain regions.

公开(公告)号：US09793378B2

公开(公告)日：2017-10-17

申请号：US13906677

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Shom Ponoth ,  Prasanna Khare ,  Qing Liu ,  Balasubramanian Pranatharthiharan

IPC: H01L29/66 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/7848 ,  H01L29/785

Abstract: Improved fin field effect transistor (FinFET) devices and methods for fabrication thereof. In one aspect, a method for fabricating a FinFET device comprises: a silicon substrate on which a silicon epitaxial layer is grown is provided. Sacrificial structures on the substrate are formed from the epitaxial layer. A blanket silicon layer is formed over the sacrificial structures and exposed substrate portions, the blanket silicon layer having upper and lower portions of uniform thickness and intermediate portions interposed between the upper and lower portions of non-uniform thickness and having an angle of formation. An array of semiconducting fins is formed from the blanket silicon layer and a non-conformal layer formed over the blanket layer. The sacrificial structures are removed and the resulting void filled with isolation structures under the channel regions. Source and drain are formed in the source/drain regions during a fin merge of the FinFET.

公开(公告)号：US09666670B2

公开(公告)日：2017-05-30

申请号：US15169473

申请日：2016-05-31

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing Liu ,  Thomas Skotnicki

IPC: H01L29/78 ,  H01L29/423 ,  H01L29/06 ,  H01L27/12 ,  H01L29/10 ,  H01L29/66 ,  H01L29/08 ,  H01L21/28

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.