公开(公告)号：US08916794B2

公开(公告)日：2014-12-23

申请号：US10551356

申请日：2004-03-29

申请人： Katsumi Yamaguchi ,  Hiroshi Nakamura

发明人： Katsumi Yamaguchi ,  Hiroshi Nakamura

IPC分类号： B23K10/00 ,  B22F9/08 ,  C21C5/46 ,  H05K3/34

CPC分类号： B22F9/082 ,  B22F2009/088 ,  H05K3/3468

摘要： A metal jet apparatus comprises a discharge nozzle 31 for jetting molten metal 20, and a gas passage 33 for supplying inert gas to a peripheral portion of a discharge port 32 of the discharge nozzle 31. The discharge port 32 of the discharge nozzle 31 and an outlet of a gas passage 33 are provided with a nozzle cover 34. The nozzle cover 34 includes a space 35 which is in communication with the discharge port 32 and the outlet of the gas passage 33, and which opens downward. A ring-like projection 36 is disposed around the opening. When the molten metal 20 is jetted from the discharge port 32 into the space 35, the inert gas is supplied to the space 35, thereby preventing the molten metal 20 from being oxidized, and it is possible to prevent the nozzle of the discharge port 32 from being clogged, and to form the molten metal 20 into a spherical shape.

摘要翻译： 金属喷射装置包括用于喷射熔融金属20的排出喷嘴31和用于向排出喷嘴31的排出口32的周边部分供给惰性气体的气体通道33.排出喷嘴31的排出口32和 气体通道33的出口设置有喷嘴盖34.喷嘴盖34包括与排出口32和气体通道33的出口连通并且向下开口的空间35。 环形突起36设置在开口周围。 当熔融金属20从排出口32喷射到空间35中时，惰性气体被供应到空间35，从而防止熔融金属20被氧化，并且可以防止排出口32的喷嘴 从而被堵塞，并将熔融金属20形成为球形。

公开(公告)号：US08665661B2

公开(公告)日：2014-03-04

申请号：US13589523

申请日：2012-08-20

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C8/00

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

摘要翻译： 提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。 第一块由具有存储单元的第一存储单元单元构成，第二块由具有存储单元的第二存储单元单元构成，并且存储单元阵列通过在其两端部排列第一块而构成， 在其他部分的第二块。 存储单元阵列的端侧上的第一存储单元单元的结构与第二存​​储单元单元不同。 用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

公开(公告)号：US20130332112A1

公开(公告)日：2013-12-12

申请号：US14000487

申请日：2011-03-01

申请人： Hiroshi Nakamura

发明人： Hiroshi Nakamura

IPC分类号： G06F17/18

CPC分类号： G06F17/18 ,  G01S17/66 ,  G01S17/936 ,  G08G1/165 ,  G08G1/166

摘要： Disclosed is a state estimation device capable of estimating the state of an observation target with high accuracy. A state estimation device performs Kalman filter update processing for applying measured data of a target vehicle by a LIDAR to a state estimation model so as to estimate the state of a vehicle near the host vehicle. The state estimation device changes the state estimation model for use in the Kalman filter update processing on the basis of the positional relationship with the target vehicle or the state of the target vehicle.

摘要翻译： 公开了能够高精度地估计观察对象物的状态的状态估计装置。 状态估计装置执行卡尔曼滤波器更新处理，用于将目标车辆的测量数据应用于状态估计模型，以便估计本车辆附近的车辆的状态。 状态估计装置基于与目标车辆的位置关系或目标车辆的状态改变用于卡尔曼滤波器更新处理的状态估计模型。

公开(公告)号：US08536959B1

公开(公告)日：2013-09-17

申请号：US13589531

申请日：2012-08-20

申请人： Eiji Mugiya ,  Tetsuo Saji ,  Takashi Matsuda ,  Hiroshi Nakamura

发明人： Eiji Mugiya ,  Tetsuo Saji ,  Takashi Matsuda ,  Hiroshi Nakamura

IPC分类号： H03H9/00 ,  H01L41/00

CPC分类号： H03H9/6483 ,  H03H9/02897 ,  H03H9/0538 ,  H03H9/1085 ,  H05K1/0271 ,  H05K1/056 ,  H05K1/185 ,  H05K3/4644

摘要： Provided is a substrate with a built-in electronic component that can minimize occurrence of functional anomaly, damage, or the like in a filter function section of an elastic wave filter that is caused by a deformation of a hollow cover of the elastic wave filter that is built into the substrate. The substrate with a built-in electronic component includes: an SAW filter built into a substrate, a filter function section of the SAW filter being covered by a hollow cover; and a stress absorbing layer that faces the hollow cover of the SAW filter through an insulating layer in the substrate.

摘要翻译： 本发明提供一种具有内置电子部件的基板，其能够使由弹性波滤波器的中空盖的变形引起的弹性波滤波器的滤波器功能部中的功能异常，损伤等的发生最小化， 内置于基材中。 具有内置电子部件的基板包括：内置于基板的SAW滤波器，SAW滤波器的滤波器功能部分被中空盖覆盖; 以及通过基板中的绝缘层面向SAW滤波器的中空盖的应力吸收层。

公开(公告)号：US08485444B2

公开(公告)日：2013-07-16

申请号：US13018814

申请日：2011-02-01

申请人： Hiroshi Nakamura

发明人： Hiroshi Nakamura

IPC分类号： G06K7/10

CPC分类号： G06K7/14

摘要： An apparatus and method for reading symbol information enabling improvement of decoding accuracy, not being affected by the condition of a reflection coefficient waveform of a reflected light beam and the kind of symbol information to be read. The method includes: reading a reflected light beam from symbol information irradiated with a light beam; detecting peak values in a reflection coefficient waveform of the reflected light beam; calculating a first peak value according to a peak value at a high reflection coefficient side (white level) among the peak values detected; calculating a second peak value according to a peak value at a low reflection coefficient side (black level) among the peak values detected; and calculating a binarization threshold based on the first peak value and the second peak value.

摘要翻译： 一种用于读取能够改善解码精度的装置和方法，不受反射光束的反射系数波形的条件和要读取的符号信息的种类的影响。 该方法包括：从用光束照射的符号信息读取反射光束; 检测反射光束的反射系数波形中的峰值; 根据所检测的峰值中的高反射系数侧（白电平）的峰值计算第一峰值; 根据所检测的峰值中的低反射系数侧（黑电平）的峰值计算第二峰值; 以及基于所述第一峰值和所述第二峰值计算二值化阈值。

公开(公告)号：US20130033275A1

公开(公告)日：2013-02-07

申请号：US13483206

申请日：2012-05-30

申请人： Hiroshi Nakamura

发明人： Hiroshi Nakamura

IPC分类号： G01R27/26 ,  G01N27/22

CPC分类号： G01N33/2852 ,  G01N27/226

摘要： A first electrode has a fuel passage. A second electrode defines a predetermined gap with the first electrode in the fuel passage. A third electrode defines a predetermined gap with the second electrode in the fuel passage. The first electrode and the second electrode form a first capacitance therebetween. The second electrode and the third electrode form a second capacitance therebetween. A circuit portion is configured to compute a property of fuel in the fuel passage according to the first capacitance and the second capacitance.

摘要翻译： 第一电极具有燃料通道。 第二电极在燃料通道中与第一电极限定预定的间隙。 第三电极在燃料通道中与第二电极限定预定的间隙。 第一电极和第二电极在它们之间形成第一电容。 第二电极和第三电极之间形成第二电容。 电路部分被配置为根据第一电容和第二电容来计算燃料通道中的燃料的特性。

公开(公告)号：US08335125B2

公开(公告)日：2012-12-18

申请号：US13285099

申请日：2011-10-31

申请人： Takeshi Nakano ,  Hiroshi Nakamura ,  Koji Hosono

发明人： Takeshi Nakano ,  Hiroshi Nakamura ,  Koji Hosono

IPC分类号： G11C8/00

CPC分类号： G11C16/08

摘要： A semiconductor memory device includes a transfer circuit and a control circuit. The transfer circuit which includes a p-type MOS transistor with a source to which is applied a first voltage and an n-type MOS transistor to whose gate the drain of the p-type MOS transistor is connected and the first voltage is transferred, to whose source a second voltage is applied, and whose drain is connected to a load. The control circuit which turns the p-type MOS transistor on and off and which turns the p-type MOS transistor on to make the p-type MOS transistor transfer the second voltage to the load and, during the transfer, turns the p-type MOS transistor off to make the gate of the n-type MOS transistor float at the first voltage.

摘要翻译： 半导体存储器件包括转移电路和控制电路。 该传输电路包括一个p型MOS晶体管，其源极被施加第一电压，一个n型MOS晶体管被连接到p型MOS晶体管的漏极并且第一个电压被传输到其栅极，到 其源极施加第二电压，并且其漏极连接到负载。 控制电路使p型MOS晶体管导通和关断，并使p型MOS晶体管导通，使p型MOS晶体管将第二电压转移到负载，并且在传输期间使p型MOS晶体管转换为p型 MOS晶体管关闭，使n型MOS晶体管的栅极浮在第一电压。

公开(公告)号：US20120314497A1

公开(公告)日：2012-12-13

申请号：US13589523

申请日：2012-08-20

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C16/04

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

摘要翻译： 提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。 第一块由具有存储单元的第一存储单元单元构成，第二块由具有存储单元的第二存储单元单元构成，并且存储单元阵列通过在其两端部排列第一块而构成， 在其他部分的第二块。 存储单元阵列的端侧上的第一存储单元单元的结构与第二存​​储单元单元不同。 用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。

公开(公告)号：US08257601B2

公开(公告)日：2012-09-04

申请号：US13073618

申请日：2011-03-28

申请人： Seiichi Kaise ,  Noriyuki Iwabuchi ,  Shigeaki Kato ,  Hiroshi Nakamura ,  Takeshi Yokouchi ,  Mariko Shibata ,  Akira Obi

发明人： Seiichi Kaise ,  Noriyuki Iwabuchi ,  Shigeaki Kato ,  Hiroshi Nakamura ,  Takeshi Yokouchi ,  Mariko Shibata ,  Akira Obi

IPC分类号： C23F1/00

CPC分类号： H01L21/67748 ,  H01J37/32743 ,  H01L21/67201 ,  H01L21/6831

摘要： A substrate processing method is used for a substrate processing system having a substrate processing device and a substrate transfer device. The substrate processing method includes a substrate transfer step of transferring a substrate and a substrate processing step of performing a predetermined process on the substrate. The substrate transfer step and the substrate processing step include a plurality of operations, and at least two operations among the plurality of the operations are performed simultaneously. Preferably, the substrate processing device includes an accommodating chamber, a mounting table placed in the accommodating chamber to be mounted thereon the substrate, and a heat transfer gas supply line for supplying a heat transfer gas to a space between the substrate mounted on the mounting table and the mounting table.

摘要翻译： 基板处理方法用于具有基板处理装置和基板转印装置的基板处理系统。 基板处理方法包括将基板转印的基板转印步骤和对基板执行预定处理的基板处理步骤。 基板转印步骤和基板处理步骤包括多个操作，并且同时执行多个操作中的至少两个操作。 优选地，基板处理装置包括容纳室，放置在容纳室中以安装在基板上的安装台，以及用于将传热气体供应到安装在安装台上的基板之间的空间的传热气体供应管线 和安装台。

公开(公告)号：US08248849B2

公开(公告)日：2012-08-21

申请号：US12855481

申请日：2010-08-12

申请人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

发明人： Hiroshi Nakamura ,  Ken Takeuchi ,  Hideko Oodaira ,  Kenichi Imamiya ,  Kazuhito Narita ,  Kazuhiro Shimizu ,  Seiichi Aritome

IPC分类号： G11C11/34

CPC分类号： G11C5/063 ,  G11C16/0483 ,  G11C16/08 ,  G11C2029/0403 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A semiconductor memory device capable of preventing a defect caused by lowering the etching precision in an end area of the memory cell array is provided. A first block is constructed by first memory cell units each having of memory cells, a second block is constructed by second memory cell units each having a plurality of memory cells, and the memory cell array is constructed by arranging the first blocks on both end portions thereof and arranging the second blocks on other portions thereof. The structure of the first memory cell unit on the end side of the memory cell array is different from that of the second memory cell unit. Wirings for connecting the selection gate lines of the memory cell array to corresponding transistors in a row decoder are formed of wiring layers formed above wirings for connecting control gate lines of the memory cell array to the transistors in the row decoder.

摘要翻译： 提供了能够防止由于降低存储单元阵列的端部区域中的蚀刻精度而导致的缺陷的半导体存储器件。 第一块由具有存储单元的第一存储单元单元构成，第二块由具有多个存储单元的第二存储单元单元构成，并且存储单元阵列通过将第一块布置在两端部 并且将第二块布置在其另一部分上。 存储单元阵列的端侧上的第一存储单元单元的结构与第二存​​储单元单元的结构不同。 用于将存储单元阵列的选择栅极线连接到行解码器中的相应晶体管的布线由布线层形成，布线层形成在用于将存储单元阵列的控制栅极线连接到行解码器中的晶体管的布线之上。