公开(公告)号：US20200057481A1

公开(公告)日：2020-02-20

申请号：US16663658

申请日：2019-10-25

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nir Rosenzweig ,  Yoni Aizik

IPC: G06F1/324 ,  G06F1/3296

Abstract: In one embodiment, a processor includes a plurality of cores, at least two of which may execute redundantly, a configuration register to store a first synchronization domain indicator to indicate that a first core and a second core are associated with a first synchronization domain, and a power controller having a synchronization circuit to cause a dynamic adjustment to a frequency of at least one of the first and second cores to cause these cores to operate at a common frequency, based at least in part on the first synchronization domain indicator. Other embodiments are described and claimed.

公开(公告)号：US10474218B2

公开(公告)日：2019-11-12

申请号：US16223794

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F12/00 ,  G06F1/3234 ,  G06F12/0864 ,  G06F12/084 ,  G06F1/28 ,  G06F12/0802 ,  G06F1/3287 ,  G06F12/0846

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US20190235618A1

公开(公告)日：2019-08-01

申请号：US16382311

申请日：2019-04-12

Applicant: Intel Corporation

Inventor： Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nir Rosenzweig ,  Eric Distefano ,  Ishmael F. Santos ,  James G. Hermerding, II

IPC: G06F1/3296 ,  G06F1/3228 ,  G06F9/30

CPC classification number: G06F1/3296 ,  G06F1/3228 ,  G06F1/324 ,  G06F9/30101 ,  G06F9/30145

Abstract: In one embodiment, a processor includes at least one core to execute instructions and a power controller coupled to the at least one core. The power controller may include a first logic to cause the at least one core to exit an idle state and enter into a maximum performance state for a first time duration, thereafter enter into an intermediate power state for a second time duration, and thereafter enter into a sustained performance state. Other embodiments are described and claimed.

公开(公告)号：US20190205061A1

公开(公告)日：2019-07-04

申请号：US15858878

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Eliezer Weissmann ,  Alexander Gendler ,  Efraim Rotem ,  Moshe Cohen ,  Asit K. Mallick ,  Jason W. Brandt ,  Kameswar Subramaniam ,  Nathan Fellman ,  Hisham Shafi

IPC: G06F3/06 ,  G06F9/30

CPC classification number: G06F3/0659 ,  G06F3/0611 ,  G06F3/0673 ,  G06F9/30098 ,  G06F9/4406 ,  G06F9/45558 ,  G06F2009/45583

Abstract: Processor, method, and system for reducing latency in accessing remote registers is described herein. One embodiment of a processor includes one or more remote registers and remote register access circuitry. The remote register access circuitry is to detect a request from the requestor to access a first register of the one or more remote registers, access to the first register in accordance to the request without the requestor having to wait for completion of the access, and provide a notification accessible to the requestor upon completion of the access to the first register of the one or more remote registers.

公开(公告)号：US10289514B2

公开(公告)日：2019-05-14

申请号：US14319197

申请日：2014-06-30

Applicant: Intel Corporation

Inventor： Dorit Shapira ,  Krishnakanth V. Sistla ,  Efraim Rotem ,  Eric Distefano ,  James G. Hermerding, II ,  Esfir Natanzon

IPC: G06F11/30 ,  G06F11/34 ,  G06F1/324 ,  G06F1/3296 ,  G01R31/28

Abstract: An apparatus and method for a user configurable reliability control loop. For example, one embodiment of a processor comprises: a reliability meter to track accumulated stress on components of the processor based on measured processor operating conditions; and a controller to receive stress rate limit information and to responsively specify a set of N operating limits on the processor in accordance with the accumulated stress and the stress rate limit information; and performance selection logic to output one or more actual operating conditions for the processor based on the N operating limits specified by the controller.

公开(公告)号：US20190102221A1

公开(公告)日：2019-04-04

申请号：US15720296

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Vijay Dhanraj ,  Russell J. Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen H. Gunter ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F9/30

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.

公开(公告)号：US10228755B2

公开(公告)日：2019-03-12

申请号：US15281806

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Efraim Rotem ,  Avinash N. Ananthakrishnan ,  Ankush Varma ,  Assaf Ganor ,  Nir Rosenzweig ,  David M. Pawlowski ,  Arik Gihon ,  Nadav Shulman

IPC: G06F1/28 ,  G06F1/32 ,  G06F1/3296

Abstract: In an embodiment, a processor includes a power control unit and a plurality of components. A first component of the plurality of components is to receive a power input from a power supply device. The power control unit is to: determine a received voltage at a power input terminal of the first component; determine a voltage difference between the received voltage of the first component and a reliability goal voltage of the first component; determine a running average value based on the voltage difference; and adjust a supply voltage of the power supply device based on the running average value. Other embodiments are described and claimed.

公开(公告)号：US10203742B2

公开(公告)日：2019-02-12

申请号：US15290619

申请日：2016-10-11

Applicant: Intel Corporation

Inventor： Gregory Sizikov ,  Michael Zelikson ,  Efraim Rotem ,  Eyal Fayneh

IPC: G06F1/00 ,  G06F1/26 ,  G06F1/32 ,  G05F3/08 ,  H02M3/158

Abstract: Described herein is an integrated circuit which comprises: a switching voltage regulator (SVR), having one or more bridge drivers, to provide regulated power supply to a plurality of power domains; and a power control unit (PCU) operable to adjust switching frequencies of the SVR according to states of the plurality of power domains, wherein drive strength or active phase count of the one or more bridge drivers is also adjusted by a logic unit of the SVR when the switching frequencies of the SVR are adjusted.

公开(公告)号：US20190041944A1

公开(公告)日：2019-02-07

申请号：US16013142

申请日：2018-06-20

Applicant: Intel Corporation

Inventor： Hisham Abu Salah ,  Efraim Rotem ,  Eliezer Weissmann ,  Yoni Aizik ,  Daniel D. Lederman

IPC: G06F1/32

Abstract: In one embodiment, processor includes a first core to execute instructions, and a power controller to control power consumption of the processor. The power controller may include a hardware performance state controller to control a performance state of the first core autonomously to an operating system, and calculate a target operating frequency for the performance state based at least in part on an energy performance preference hint received from the operating system. Other embodiments are described and claimed.

公开(公告)号：US20190011975A1

公开(公告)日：2019-01-10

申请号：US16044994

申请日：2018-07-25

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F1/32 ,  G06F12/0846 ,  G06F1/28 ,  G06F12/0802 ,  G06F12/084 ,  G06F12/0864

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.