公开(公告)号：US20120021604A1

公开(公告)日：2012-01-26

申请号：US12841874

申请日：2010-07-22

Applicant: Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

Inventor： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

IPC: H01L21/306 ,  H01L21/302 ,  H01L21/3065

CPC classification number: H01L21/6835 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed.

Abstract translation: 一种方法包括通过粘合剂将晶片接合在载体上，并在晶片上进行稀化处理。 在进行稀化处理的步骤之后，去除未被晶片覆盖的粘合剂的一部分，同时由晶片覆盖的粘合剂部分未被除去。

公开(公告)号：US08058692B2

公开(公告)日：2011-11-15

申请号：US12345332

申请日：2008-12-29

Applicant: Li-Shyue Lai ,  Jing-Cheng Lin

Inventor： Li-Shyue Lai ,  Jing-Cheng Lin

IPC: H01L29/786

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/165 ,  H01L29/66795

Abstract: A method of forming an integrated circuit structure includes forming a first insulation region and a second insulation region in a semiconductor substrate and facing each other; and forming an epitaxial semiconductor region having a reversed T-shape. The epitaxial semiconductor region includes a horizontal plate including a bottom portion between and adjoining the first insulation region and the second insulation region, and a fin over and adjoining the horizontal plate. The bottom of the horizontal plate contacts the semiconductor substrate. The method further includes forming a gate dielectric on a top surface and at least top portions of sidewalls of the fin; and forming a gate electrode over the gate dielectric.

Abstract translation: 形成集成电路结构的方法包括：在半导体衬底中形成第一绝缘区域和第二绝缘区域并彼此面对; 以及形成具有反向T形的外延半导体区域。 外延半导体区域包括水平板，该水平板包括在第一绝缘区域和第二绝缘区域之间并邻接第一绝缘区域之间的底部，以及在水平板上并邻接的鳍状物。 水平板的底部接触半导体衬底。 该方法还包括在鳍的顶表面和至少顶部的顶部形成栅电介质; 以及在所述栅极电介质上形成栅电极。

公开(公告)号：US20110163599A1

公开(公告)日：2011-07-07

申请号：US12683412

申请日：2010-01-06

Applicant: Ching-Shan Leu ,  Jing-Cheng Lin ,  Shun-Yuan Wu

Inventor： Ching-Shan Leu ,  Jing-Cheng Lin ,  Shun-Yuan Wu

IPC: H02M3/156

CPC classification number: H02M3/155 ,  H02M3/158 ,  H02M2001/009 ,  Y10T307/406

Abstract: A high voltage gain power converter includes: a main switch element; an assistant switch element; a first inductive element, a first switch element, and a first capacitive element; and a second inductive element, a second switch element, and a second capacitive element. The first inductive element is connected between an input node and first switch element. The first capacitive element, connected between the first switch element and ground, provides a first boost output voltage. The second inductive element is connected between the main switch element and first capacitive element. The second switch element is connected to a common node of the second inductive element and main switch element. The second capacitive element, connecting the second switch element to a first node, provides a second boost output voltage. The assistant switch element is connected between the first inductive element and common node of the second inductive element and main switch element.

Abstract translation: 高压增益功率转换器包括：主开关元件; 辅助开关元件; 第一电感元件，第一开关元件和第一电容元件; 以及第二感应元件，第二开关元件和第二电容元件。 第一电感元件连接在输入节点和第一开关元件之间。 连接在第一开关元件和地之间的第一电容元件提供第一升压输出电压。 第二电感元件连接在主开关元件和第一电容元件之间。 第二开关元件连接到第二电感元件和主开关元件的公共节点。 将第二开关元件连接到第一节点的第二电容元件提供第二升压输出电压。 辅助开关元件连接在第二电感元件和主开关元件的第一电感元件和公共节点之间。

公开(公告)号：US07226860B2

公开(公告)日：2007-06-05

申请号：US10833154

申请日：2004-04-28

Applicant: Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

Inventor： Hsien-Ming Lee ,  Jing-Cheng Lin ,  Shing-Chyang Pan ,  Ming-Hsing Tsai ,  Hung-Wen Su ,  Shih-Wei Chou ,  Shau-Lin Shue ,  Kuo-Wei Cheng ,  Ting-Chu Ko

IPC: H01L21/44

CPC classification number: H01L21/2885 ,  H01L21/76843 ,  H01L21/76861 ,  H01L21/76862 ,  H01L21/76873 ,  H01L21/76877

Abstract: A method of electrochemical deposition (ECD) provides a barrier and a seed layer on a substrate. The surfaces of the substrate are pre-treated before a metal layer is electrochemically deposited thereon in an electrochemical plating cell with a physical or a chemical surface treatment process. The electrochemical plating cell is covered by a cap to prevent evaporation of the electrolyte solution. The electrochemical plating cell includes a substrate holder assembly with a lift seal, e.g., with a contact angle θ less than 90° between the lift seal and the substrate. The substrate holder assembly includes a substrate chuck at the rear side of the substrate.

公开(公告)号：US07215024B2

公开(公告)日：2007-05-08

申请号：US10936922

申请日：2004-09-08

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Shau-Lin Shue ,  Mong-Song Liang

IPC: H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/32051 ,  H01L21/32136 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76888 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A new method is provided for the creation of a barrier-free copper interconnect. A dual damascene structure is created in a layer of dielectric, a thin metal barrier layer is deposited. The metal barrier layer is oxidized, two layers are then deposited with the first layer comprising doped copper and the second layer comprising pure copper. The dual damascene structure is filled with copper, a thermal anneal is applied, stabilizing the deposited copper filling the dual damascene structure and forming metal oxide of the doped minority element. Excess copper is then removed from the dielectric.

Abstract translation: 提供了一种创建无障碍铜互连的新方法。 在电介质层中形成双镶嵌结构，沉积薄金属阻挡层。 金属阻挡层被氧化，然后沉积两层，第一层包含掺杂的铜，第二层包含纯铜。 双镶嵌结构填充铜，进行热退火，稳定沉积的铜填充双镶嵌结构并形成掺杂少数元素的金属氧化物。 然后从电介质中除去过量的铜。

公开(公告)号：US07030023B2

公开(公告)日：2006-04-18

申请号：US10655972

申请日：2003-09-04

Applicant: Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

Inventor： Shing-Chyang Pan ,  Ching-Hua Hsieh ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Shau-Lin Shue

IPC: H01L21/302

CPC classification number: H01L21/3105 ,  H01L21/28556 ,  H01L21/76807 ,  H01L21/76814 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76873

Abstract: A method for forming a copper damascene feature including providing a semiconductor process wafer including at least one via opening formed to extend through a thickness of at least one dielectric insulating layer and an overlying trench line opening encompassing the at least one via opening to form a dual damascene opening; etching through an etch stop layer at the at least one via opening bottom portion to expose an underlying copper area; carrying out a sub-atmospheric DEGAS process with simultaneous heating of the process wafer in a hydrogen containing ambient; carrying out an in-situ sputter-clean process; and, forming a barrier layer in-situ to line the dual damascene opening.

Abstract translation: 一种用于形成铜镶嵌特征的方法，包括提供半导体工艺晶片，其包括形成为延伸穿过至少一个介电绝缘层的厚度的至少一个通孔开口，以及覆盖所述至少一个通孔开口的上覆沟槽开口，以形成双重 大马士革开幕 在所述至少一个通孔开口底部处蚀刻通过蚀刻停止层以暴露下面的铜区域; 在含氢环境中同时加热工艺晶片，进行亚低温DEGAS工艺; 进行原位溅射清洗过程; 并且原位形成阻挡层以使双镶嵌开口成线。

公开(公告)号：US06943111B2

公开(公告)日：2005-09-13

申请号：US10361732

申请日：2003-02-10

Applicant: Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

Inventor： Jing-Cheng Lin ,  Cheng-Lin Huang ,  Winston Shue ,  Mong-Song Liang

IPC: H01L21/768 ,  H01L21/4763 ,  H01L21/302 ,  H01L21/44

CPC classification number: H01L21/76843 ,  H01L21/76855 ,  H01L21/76864 ,  H01L21/76873 ,  H01L2221/1089

Abstract: A new method is provided for the creation of a copper seed interface capability. A first seed layer of copper alloy and a second seed layer of copper is provided over an opening in a layer of dielectric. The opening is filled with copper, the first and second seed layers are annealed.

Abstract translation: 提供了一种用于创建铜种子界面能力的新方法。 在介电层中的开口上方设置有铜合金的第一籽晶层和铜的第二晶种层。 开口填充有铜，第一和第二种子层被退火。

公开(公告)号：US20050189075A1

公开(公告)日：2005-09-01

申请号：US10789660

申请日：2004-02-27

Applicant: Shing-Chyang Pan ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Li-Lin Su ,  Shau-Lin Shue

Inventor： Shing-Chyang Pan ,  Jing-Cheng Lin ,  Hsien-Ming Lee ,  Cheng-Lin Huang ,  Ching-Hua Hsieh ,  Chao-Hsien Peng ,  Li-Lin Su ,  Shau-Lin Shue

IPC: B08B7/00 ,  H01J37/32 ,  H01L21/00 ,  C23F1/00

CPC classification number: H01L21/67109 ,  B08B7/0071 ,  H01J37/32862

Abstract: A reactive pre-clean chamber that contains a wafer heating apparatus, such as a high-temperature electrostatic chuck (HTESC), for directly heating a wafer supported on the apparatus during a pre-cleaning process. The wafer heating apparatus is capable of heating the wafer to the optimum temperatures required for a hydrogen plasma reactive pre-clean (RPC) process. Furthermore, degassing and pre-cleaning can be carried out in the same pre-clean chamber. The invention further includes a method of pre-cleaning a wafer using a pre-clean chamber that contains a wafer heating apparatus.

Abstract translation: 一种反应性预清洁室，其包含诸如高温静电卡盘（HTESC）的晶片加热装置，用于在预清洁过程期间直接加热支撑在装置上的晶片。 晶片加热装置能够将晶片加热到氢等离子体反应性预清洁（RPC）工艺所需的最佳温度。 此外，脱气和预清洁可以在相同的预清洁室中进行。 本发明还包括使用包含晶片加热装置的预清洁室预清洁晶片的方法。

公开(公告)号：US20050023686A1

公开(公告)日：2005-02-03

申请号：US10918816

申请日：2004-08-13

Applicant: Jing-Cheng Lin

Inventor： Jing-Cheng Lin

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC classification number: H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

Abstract: It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400° C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400° C.

Abstract translation: 本发明的一般目的是提供一种改进的制造方法，该方法是在单和双镶嵌互连沟槽/接触通孔加工中具有以下结构的W / WSiN / WN结构的改进的铜金属扩散阻挡层的形成 微米节点用于MOSFET和CMOS应用。 扩散阻挡层通过沉积氮化钨底层，随后形成SiH4 / NH3或SiH4 / H2浸泡形成WSiN层，并沉积钨的最终顶层形成。 本发明用于在逻辑和存储器应用的MOSFET和CMOS器件的制造中制造可靠的金属互连和接触孔，并且形成的铜扩散阻挡层W / WSiN / WN在400℃下通过严格的阻挡热可靠性测试 在400℃的严格的阻隔热可靠性试验期间，纯单层阻挡层，即单层WN，表现出铜冲穿或铜尖峰。

公开(公告)号：US06797608B1

公开(公告)日：2004-09-28

申请号：US09587465

申请日：2000-06-05

Applicant: Jing-Cheng Lin

Inventor： Jing-Cheng Lin

IPC: H01L214763

CPC classification number: H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L2924/0002 ,  H01L2924/00

Abstract: It is a general object of the present invention to provide an improved method of fabrication in the formation of an improved copper metal diffusion barrier layer having the structure, W/WSiN/WN, in single and dual damascene interconnect trench/contact via processing with 0.10 micron nodes for MOSFET and CMOS applications. The diffusion barrier is formed by depositing a tungsten nitride bottom layer, followed by an in situ SiH4/NH3 or SiH4/H2 soak forming a WSiN layer, and depositing a final top layer of tungsten. This invention is used to manufacture reliable metal interconnects and contact vias in the fabrication of MOSFET and CMOS devices for both logic and memory applications and the copper diffusion barrier formed, W/WSiN/WN, passes a stringent barrier thermal reliability test at 400° C. Pure single barrier layers, i.e., single layer WN, exhibit copper punch through or copper spiking during the stringent barrier thermal reliability test at 400° C.

Abstract translation: 本发明的一般目的是提供一种改进的制造方法，该方法是在单和双镶嵌互连沟槽/接触通孔加工中具有以下结构的W / WSiN / WN结构的改进的铜金属扩散阻挡层的形成 微米节点用于MOSFET和CMOS应用。 扩散阻挡层通过沉积氮化钨底层，随后形成SiH4 / NH3或SiH4 / H2浸泡形成WSiN层，并沉积钨的最终顶层形成。 本发明用于在逻辑和存储器应用的MOSFET和CMOS器件的制造中制造可靠的金属互连和接触孔，并且形成的铜扩散阻挡层W / WSiN / WN在400℃下通过严格的阻挡热可靠性测试 在400℃的严格的阻隔热可靠性试验期间，纯单层阻挡层，即单层WN，表现出铜冲穿或铜尖峰。