公开(公告)号：US20220336021A1

公开(公告)日：2022-10-20

申请号：US17857942

申请日：2022-07-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Steve Kientz

IPC: G11C16/10 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G06F12/02 ,  G06F12/0882 ,  G11C16/34

Abstract: A first bin boundary for a first voltage bin associated with a die of a memory device is identified. The first bin boundary corresponds to a first block family associated with the first voltage bin. A first bin boundary offset between the first block family and a second block family is determined. The first bin boundary is updated based on the first bin boundary offset.

公开(公告)号：US20220334721A1

公开(公告)日：2022-10-20

申请号：US17846378

申请日：2022-06-22

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Peter Feeley ,  Larry J. Koudele ,  Shane Nowell ,  Steven Michael Kientz

IPC: G06F3/06

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to perform operations comprising assigning a plurality of data streams to a block family comprising a plurality of blocks of a memory device; responsive to programming a first block associated with a first data stream of the plurality of data streams, associating the first block with the block family; and responsive to programming a second block associated with a second data stream of the plurality of data streams, associating the second block with the block family.

公开(公告)号：US20220319630A1

公开(公告)日：2022-10-06

申请号：US17217780

申请日：2021-03-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Sheperek ,  Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Larry J. Koudele

IPC: G11C29/56 ,  G11C16/26

Abstract: A method can include receiving a request to read data from a block of a memory device coupled with a processing device, determining, using a first data structure mapping block identifiers to corresponding block family identifiers, a block family associated with the block of the memory device, determining, using a second data structure mapping block family identifiers to corresponding voltage distribution parameter values, a voltage distribution parameter value associated with the block family, determining a set of read levels associated with the voltage distribution parameter value, wherein each read level in the set of read levels corresponds to a respective voltage distribution of at least one memory cell comprised by the block of the memory device, and reading, using the determined set of read levels, data from the block of the memory device.

公开(公告)号：US20220284967A1

公开(公告)日：2022-09-08

申请号：US17826775

申请日：2022-05-27

Applicant: Micron Technology, Inc.

Inventor： Bruce A. Liikanen ,  Michael Sheperek ,  Larry J. Koudele

IPC: G11C16/14 ,  G11C16/12 ,  G11C16/34 ,  G06F11/07

Abstract: A system includes a memory array with memory cells and a processing device coupled thereto. The processing device performs program targeting operations that include to: determine a set of difference error counts corresponding to programming distributions of the memory array; identify, based on a comparison of the set of difference error counts, valley margins corresponding to the programming distributions; select, based on values of the valley margins, a program targeting rule from a set of rules; perform, based on the program targeting rule, a program targeting operation to adjust a voltage level associated with an erase distribution of the memory array; determine a bit error rate (BER) of the memory array; in response to the BER satisfying a BER control value, reduce the voltage level by a voltage step; and in response to the BER not satisfying the BER control value, increase the voltage level by the voltage step.

公开(公告)号：US20220276784A1

公开(公告)日：2022-09-01

申请号：US17744563

申请日：2022-05-13

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Vamsi Pavan Rayaprolu ,  Shane Nowell ,  Michael Sheperek

IPC: G06F3/06

Abstract: A system can include a memory device and a processing device to perform operations that include performing, at a first frequency, a calibration scan, where the calibration scan includes calibrating block family-to-bin associations for one or more younger voltage bins based on first measurement data determined by the calibration scan, and calibrating block family-to-bin associations for one or more older voltage bins based on second measurement data provided by a media management scan, where the media management scan is performed at a second frequency, such that the second frequency is lower than the first frequency, each of the younger voltage bins satisfies a first age threshold criterion, and each of the older voltage bins satisfies a second age threshold criterion.

公开(公告)号：US11416173B2

公开(公告)日：2022-08-16

申请号：US16850224

申请日：2020-04-16

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Steve Kientz

IPC: G06F3/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/04

Abstract: A memory device includes a processing device configured to iteratively update a center read level according to a first step size after reading a subset of memory cells according to a set of read levels including the center read level; track an update direction for the processing device to use when iteratively updating the center read level, wherein the update direction corresponds to an increase or a decrease in the center read level; detect a change condition based on updating the center read level according to the first step size; and iteratively update the center read level according to a second step size based on detection of the change condition.

公开(公告)号：US20220157385A1

公开(公告)日：2022-05-19

申请号：US17589491

申请日：2022-01-31

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan RAYAPROLU ,  Mustafa N. Kaynak ,  Michael Sheperek ,  Larry J. Koudele ,  Shane Nowell

IPC: G11C16/10 ,  G11C16/08 ,  G06F12/06

Abstract: One or more data units at a memory device and that are associated with one or more dice of a die group comprising a plurality of dice are programmed. A voltage offset bin associated with the plurality of dice in the die group is determined based on a subset of dice of the die group.

公开(公告)号：US20220156188A1

公开(公告)日：2022-05-19

申请号：US17667326

申请日：2022-02-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Mustafa N. Kaynak ,  Shane Nowell

IPC: G06F12/0802 ,  G06F12/06 ,  G11C16/10

Abstract: A set of two or more block families associated with a bin boundary of a first voltage bin is identified. A determination of at least a first voltage for a first block family of the plurality of block families and a second voltage for a second block family of the plurality of block families based on values of a data state metric for each of the plurality of block families. In response to a determination that a difference between the first voltage and the second voltage satisfies a block family combination criterion, the second block family is merged with the first block family.

公开(公告)号：US11309020B2

公开(公告)日：2022-04-19

申请号：US17112755

申请日：2020-12-04

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Larry J. Koudele ,  Bruce A. Liikanen

IPC: G11C16/04 ,  G11C11/56 ,  G11C5/04

Abstract: A processing device performs a multi-pass programming operation on the memory device resulting in first pass programming distributions and second pass programming distributions. One or more read level thresholds between the second pass programming distributions are changed. Responsive to changing the one or more read level thresholds between the second pass programming distributions, one or more read level thresholds between the first pass programming distributions are adjusted based on the changes to the one or more read level thresholds between the second pass programming distributions.

公开(公告)号：US11301382B2

公开(公告)日：2022-04-12

申请号：US16948774

申请日：2020-09-30

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Bruce A. Liikanen ,  Steven Michael Kientz

IPC: G06F12/0804 ,  G06F3/06 ,  G11C16/30 ,  G11C16/32 ,  G01R19/165 ,  G11C16/10 ,  G11C16/04

Abstract: A system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is to perform operations including detecting a voltage of a power source for the memory device has dropped below a threshold voltage indicative of an imminent power loss and writing data to the memory device in response to the detecting. The operations further include measuring a characteristic of the data in response to detecting a power on of the memory device; determining an estimated amount of time for which the memory device was powered off based on results of the measuring; and in response to the estimated amount of time satisfying a first threshold criterion, updating a value for a temporal voltage shift of a block family of programmed data based on the estimated amount of time.