公开(公告)号：US06782158B2

公开(公告)日：2004-08-24

申请号：US10263988

申请日：2002-10-02

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: G02B628

CPC classification number: G02B6/29355 ,  G02B6/29386 ,  H04J14/02

Abstract: A dispersion mitigating interleaver assembly has a first unbalanced Mach-Zehnder interferometer (MZI) assembly which includes first and second output ports and which has first transmission vs. wavelength curve and a first dispersion vs. wavelength curve. The dispersion mitigating interleaver assembly also includes a second unbalanced MZI assembly which has a second transmission vs. wavelength curve and a second dispersion vs. wavelength curve. The second unbalanced MZI assembly receives an output from one of the first and second output ports of the first unbalanced MZI assembly. The second transmission vs. wavelength curve is substantially the same as the first transmission vs. wavelength curve and the second dispersion vs. wavelength curve is substantially opposite with respect to the first dispersion vs. wavelength curve, such that dispersion is substantially cancelled by the cooperation of the first and second unbalanced MZI assemblies.

公开(公告)号：US06444136B1

公开(公告)日：2002-09-03

申请号：US09559292

申请日：2000-04-25

Applicant: Q. Z. Liu ,  Bin Zhao

Inventor： Q. Z. Liu ,  Bin Zhao

IPC: B44C122

CPC classification number: H01L21/02134 ,  H01L21/02351 ,  H01L21/31058 ,  H01L21/3124 ,  H01L21/76802 ,  H01L21/76825 ,  H01L21/76831

Abstract: Fabrication of improved low-k dielectric structures is disclosed. Low-k dielectric structures are fabricated while overcoming the otherwise existing problems associated with the use of low-k dielectric materials. In one embodiment, the physical properties of a low-k dielectric material is modified by exposing the low-k dielectric material to electron beams. The exposed portion of the low-k dielectric material becomes easier to etch and clean and exhibits greater mechanical strength and a reduction in absorption of moisture. In another embodiment, a number of incremental exposure and etch steps are performed to fabricate a desired structure. In yet another embodiment, the steps of exposure of a low-k dielectric material are combined with the etch steps. The exposure and the etching of the low-k dielectric material are performed concurrently in the same system. In still another embodiment, a single exposure and a single etch step are utilized to fabricate a desired structure. All the disclosed embodiments can be practiced by exposing the low-k dielectric material to ion beams instead of electron beams.

Abstract translation: 公开了改进的低k电介质结构的制造。 制造低k电介质结构，同时克服与使用低k电介质材料相关的其他现有问题。 在一个实施例中，通过将低k电介质材料暴露于电子束来修改低k电介质材料的物理性质。 低k电介质材料的暴露部分变得更容易蚀刻和清洁，并且表现出更大的机械强度和减少吸湿性。 在另一个实施例中，执行多个增量曝光和蚀刻步骤以制造期望的结构。 在另一个实施例中，将低k电介质材料的曝光步骤与蚀刻步骤组合。 在同一系统中同时进行低k电介质材料的曝光和蚀刻。 在另一个实施例中，利用单次曝光和单个蚀刻步骤来制造所需的结构。 所有公开的实施例可以通过将低k电介质材料暴露于离子束而不是电子束来实施。

公开(公告)号：US06329290B1

公开(公告)日：2001-12-11

申请号：US09512396

申请日：2000-02-24

Applicant: Bin Zhao

Inventor： Bin Zhao

IPC: H01L21311

CPC classification number: H01L21/76831 ,  H01L21/76808

Abstract: A via is first etched in a dielectric. Then a conformal layer is deposited over the dielectric and the via to reduce an initial width of the via to a target width. A trench is then etched in the dielectric and the conformal layer. Since the width of the via is reduced from the initial width to the target width, the resulting final via has a high aspect ratio. The via and the trench are then filled with metal which contacts an interconnect metal situated below the via. In one embodiment, copper is used to fill the via and the trench and also as the interconnect metal below the via. In one embodiment, the dielectric is silicon dioxide or fluorinated silicon dioxide and the conformal layer is silicon dioxide. In another embodiment, the dielectric is silicon dioxide or fluorinated silicon dioxide while the conformal layer is silicon nitride. To etch the trench in the dielectric and the conformal layer, a timed exposure to a carbon fluoride based plasma is employed. Alternatively, instead of timing the exposure to plasma, a suitable etch stop layer is used. In the embodiment where a conformal layer of high dielectric constant is used, the conformal layer remaining on the dielectric surface is removed using either chemical mechanical polishing or by plasma etching. The final structure is a via and a trench where the via's side walls are covered by the conformal layer while the trench's side walls are not covered by the conformal layer.

Abstract translation: 首先在电介质中蚀刻通孔。 然后在电介质和通孔上沉积保形层以将通孔的初始宽度减小到目标宽度。 然后在电介质和保形层中蚀刻沟槽。 由于通孔的宽度从初始宽度减小到目标宽度，所得到的最终通孔具有高纵横比。 然后，通孔和沟槽填充有与位于通孔下方的互连金属接触的金属。 在一个实施例中，铜用于填充通孔和沟槽，并且还用作通孔下方的互连金属。 在一个实施例中，电介质是二氧化硅或氟化二氧化硅，并且保形层是二氧化硅。 在另一个实施例中，电介质是二氧化硅或氟化二氧化硅，而保形层是氮化硅。 为了蚀刻电介质和共形层中的沟槽，采用了基于氟化碳的等离子体的定时曝光。 或者，代替等离子体曝光的定时，使用合适的蚀刻停止层。 在使用高介电常数的保形层的实施例中，使用化学机械抛光或通过等离子体蚀刻来去除保留在电介质表面上的保形层。 最终结构是通孔和沟槽，其中通孔的侧壁被保形层覆盖，而沟槽的侧壁不被保形层覆盖。

公开(公告)号：US6100184A

公开(公告)日：2000-08-08

申请号：US914995

申请日：1997-08-20

Applicant: Bin Zhao ,  Prahalad K. Vasudev ,  Ronald S. Horwath ,  Thomas E. Seidel ,  Peter M. Zeitzoff

Inventor： Bin Zhao ,  Prahalad K. Vasudev ,  Ronald S. Horwath ,  Thomas E. Seidel ,  Peter M. Zeitzoff

IPC: H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/4763

CPC classification number: H01L21/76849 ,  H01L21/7681 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/5329 ,  H01L2924/0002 ,  Y10S438/902

Abstract: A technique for fabricating a dual damascene interconnect structure using a low dielectric constant material as a dielectric layer or layers. A low dielectric constant (low-.di-elect cons.) dielectric material is used to form an inter-level dielectric (ILD) layer between metallization layers and in which via and trench openings are formed in the low-.di-elect cons. ILD. The dual damascene technique allows for both the via and trench openings to be filled at the same time.

Abstract translation: 一种使用低介电常数材料作为电介质层或多层制造双镶嵌互连结构的技术。 低介电常数（低+ 531）介电材料用于在金属化层之间形成层间电介质层（ILD）层，其中通孔和沟槽开口形成在低+ 531 ILD中。 双镶嵌技术允许通孔和沟槽开口同时被填充。

公开(公告)号：US5674787A

公开(公告)日：1997-10-07

申请号：US587263

申请日：1996-01-16

Applicant: Bin Zhao ,  Prahalad K. Vasudev ,  Valery M. Dubin ,  Yosef Shacham-Diamand ,  Chiu H. Ting

Inventor： Bin Zhao ,  Prahalad K. Vasudev ,  Valery M. Dubin ,  Yosef Shacham-Diamand ,  Chiu H. Ting

IPC: H01L21/288 ,  H01L21/768 ,  H01L21/28

CPC classification number: H01L21/76831 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76874 ,  H01L21/76879 ,  Y10S977/81

Abstract: A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal layer is exposed by the via opening, a SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer. The SiN or SiON sidewalls, the bottom barrier layer and the cap barrier layer function to fully encapsulate the copper plug in the via. The plug is then annealed.

Abstract translation: 一种方法或利用无电镀铜沉积来选择性地形成封装的铜塞以连接半导体上的导电区域。 层间电介质（ILD）中的通孔开口提供用于连接由ILD分离的两个导电区域的路径。 一旦底层金属层被通孔开口暴露，沿通孔的侧壁形成SiN或SiON电介质封装层。 然后，使用接触位移技术在阻挡金属上形成薄的铜活化层，例如在下面的金属层上作为覆盖层存在的TiN。 在通孔底部的阻挡层上的铜的接触位移之后，然后使用无电解铜沉积技术自动催化将铜沉积在通孔中。 无电铜沉积继续直到通孔几乎被填充，但是在顶部留下足够的空间以形成上封装层。 SiN或SiON侧壁，底部阻挡层和帽阻挡层用于将铜塞完全封装在通孔中。 然后将塞子退火。

公开(公告)号：US5660706A

公开(公告)日：1997-08-26

申请号：US688466

申请日：1996-07-30

Applicant: Bin Zhao ,  Prahalad K. Vasudev

Inventor： Bin Zhao ,  Prahalad K. Vasudev

IPC: C23C18/16 ,  H01L21/288 ,  H01L21/768 ,  C25D5/02 ,  C25D5/04 ,  C25D7/12 ,  C25D17/00

CPC classification number: H01L21/76831 ,  C23C18/1607 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1669 ,  C23C18/1671 ,  H01L21/2885 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76879

Abstract: A technique for utilizing an electric field to initiate electroless deposition of a material to form layers and/or structures on a semiconductor wafer. The wafer is disposed between a positive electrode and a negative electrode and disposed so that its deposition surface faces the positive electrode. A conductive surface on the wafer is then subjected to an electroless copper deposition solution. When copper is the conductive material being deposited, positive copper ions in the solution are repelled by the positive electrode and attracted by the negatively charged wafer surface. Once physical contact is made, the copper ions dissipate their charges by accepting electrons from the conductive surface, thereby forming copper atoms on the surface. The deposited copper have the catalytic properties so that when a reductant in the solution is absorbed at the copper sites and then oxidized, additional electrons are released into the conductive surface. The formation of the initial layer of copper functions as a seed layer for further electroless growth of copper. The same electroless deposition solution can be used for both the initial activation layer and the additional autocatalytic growth on to the seed layer.

Abstract translation: 一种利用电场来引发化学沉积材料以在半导体晶片上形成层和/或结构的技术。 晶片设置在正电极和负电极之间并且被设置为使得其沉积表面面向正电极。 然后将晶片上的导电表面经受化学镀铜沉积溶液。 当铜是导电材料沉积时，溶液中的正铜离子被正极排斥并被带负电的晶片表面吸引。 一旦进行物理接触，铜离子通过从导电表面接受电子而耗散它们的电荷，从而在表面上形成铜原子。 沉积的铜具有催化性能，使得当溶液中的还原剂在铜位置被吸收然后被氧化时，附加的电子被释放到导电表面中。 铜的初始层的形成用作用于铜的进一步无电生长的种子层。 相同的无电沉积溶液可以用于初始活化层和在种子层上的额外的自催化生长。