中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

156 records (took 0.028 seconds)

    Protected encapsulation of catalytic layer for electroless copper interconnect
    4.
    发明授权
    Protected encapsulation of catalytic layer for electroless copper interconnect 失效
    用于无电铜互连的催化层的保护封装

    公开(公告)号：US5824599A

    公开(公告)日：1998-10-20

    申请号：US587264

    申请日：1996-01-16

    Applicant: Yosef Schacham-Diamand ,  Valery M. Dubin ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev ,  Melvin Desilva

    Inventor： Yosef Schacham-Diamand ,  Valery M. Dubin ,  Chiu H. Ting ,  Bin Zhao ,  Prahalad K. Vasudev ,  Melvin Desilva

    IPC: H01L21/768 ,  H01L21/44

    CPC classification number: H01L21/76834 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76858 ,  Y10S977/712 ,  Y10S977/81 ,  Y10S977/888 ,  Y10S977/89

    Abstract: A method for utilizing electroless copper deposition to form interconnects on a semiconductor. Once a via or a trench is formed in a dielectric layer, a titanium nitride (TiN) or tantalum (Ta) barrier layer is deposited. Then, a catalytic copper seed layer is conformally blanket deposited in vacuum over the barrier layer. Next, without breaking the vacuum, an aluminum protective layer is deposited onto the catalytic layer to encapsulate and protect the catalytic layer from oxidizing. An electroless deposition technique is then used to auto-catalytically deposit copper on the catalytic layer. The electroless deposition solution dissolves the overlying protective layer to expose the surface of the underlying catalytic layer. The electroless copper deposition occurs on this catalytic surface, and continues until the via/trench is filled. Subsequently, the copper and barrier material are polished by an application of chemical-mechanical polishing (CMP) to remove excess copper and barrier material from the surface, so that the only copper and barrier material remaining are in the via/trench openings. Then an overlying silicon nitride (SiN) layer is formed above the exposed copper in order to form a dielectric barrier layer. The copper interconnect is fully encapsulated from the adjacent material by the TiN (or Ta) barrier layer and the overlying SiN layer.

    Abstract translation: 一种利用无电铜沉积在半导体上形成互连的方法。 一旦在电介质层中形成通孔或沟槽，则沉积氮化钛（TiN）或钽（Ta）阻挡层。 然后，催化铜籽晶层在真空中在阻挡层上共形地覆盖。 接下来，在不破坏真空的情况下，将铝保护层沉积到催化剂层上以包封并保护催化剂层免于氧化。 然后使用无电沉积技术在催化剂层上自动催化沉积铜。 无电沉积溶液溶解上覆的保护层以暴露下面的催化剂层的表面。 无电铜沉积发生在该催化剂表面上，并持续直到通孔/沟槽被填充。 随后，通过施加化学机械抛光（CMP）来抛光铜和阻挡材料，以从表面去除多余的铜和阻挡材料，使得剩余的唯一的铜和阻挡材料在通孔/沟槽开口中。 然后，在暴露的铜上方形成覆盖氮化硅（SiN）层，以形成电介质阻挡层。 铜互连通过TiN（或Ta）阻挡层和覆盖的SiN层从相邻材料完全封装。

    Selective electroless copper deposited interconnect plugs for ULSI applications
    7.
    发明授权
    Selective electroless copper deposited interconnect plugs for ULSI applications 失效
    用于ULSI应用的选择性无电铜沉积互连插头

    公开(公告)号：US5674787A

    公开(公告)日：1997-10-07

    申请号：US587263

    申请日：1996-01-16

    Applicant: Bin Zhao ,  Prahalad K. Vasudev ,  Valery M. Dubin ,  Yosef Shacham-Diamand ,  Chiu H. Ting

    Inventor： Bin Zhao ,  Prahalad K. Vasudev ,  Valery M. Dubin ,  Yosef Shacham-Diamand ,  Chiu H. Ting

    IPC: H01L21/288 ,  H01L21/768 ,  H01L21/28

    CPC classification number: H01L21/76831 ,  H01L21/288 ,  H01L21/76849 ,  H01L21/76874 ,  H01L21/76879 ,  Y10S977/81

    Abstract: A method or utilizing electroless copper deposition to selectively form encapsulated copper plugs to connect conductive regions on a semiconductor. A via opening in an inter-level dielectric (ILD) provides a path for connecting two conductive regions separated by the ILD. Once the underlying metal layer is exposed by the via opening, a SiN or SiON dielectric encapsulation layer is formed along the sidewalls of the via. Then, a contact displacement technique is used to form a thin activation layer of copper on a barrier metal, such as TiN, which is present as a covering layer on the underlying metal layer. After the contact displacement of copper on the barrier layer at the bottom of the via, an electroless copper deposition technique is then used to auto-catalytically deposit copper in the via. The electroless copper deposition continues until the via is almost filled, but leaving sufficient room at the top in order to form an upper encapsulation layer. The SiN or SiON sidewalls, the bottom barrier layer and the cap barrier layer function to fully encapsulate the copper plug in the via. The plug is then annealed.

    Abstract translation: 一种方法或利用无电镀铜沉积来选择性地形成封装的铜塞以连接半导体上的导电区域。 层间电介质（ILD）中的通孔开口提供用于连接由ILD分离的两个导电区域的路径。 一旦底层金属层被通孔开口暴露，沿通孔的侧壁形成SiN或SiON电介质封装层。 然后，使用接触位移技术在阻挡金属上形成薄的铜活化层，例如在下面的金属层上作为覆盖层存在的TiN。 在通孔底部的阻挡层上的铜的接触位移之后，然后使用无电解铜沉积技术自动催化将铜沉积在通孔中。 无电铜沉积继续直到通孔几乎被填充，但是在顶部留下足够的空间以形成上封装层。 SiN或SiON侧壁，底部阻挡层和帽阻挡层用于将铜塞完全封装在通孔中。 然后将塞子退火。

    Electric field initiated electroless metal deposition
    8.
    发明授权
    Electric field initiated electroless metal deposition 失效
    电场引发无电金属沉积

    公开(公告)号：US5660706A

    公开(公告)日：1997-08-26

    申请号：US688466

    申请日：1996-07-30

    Applicant: Bin Zhao ,  Prahalad K. Vasudev

    Inventor： Bin Zhao ,  Prahalad K. Vasudev

    IPC: C23C18/16 ,  H01L21/288 ,  H01L21/768 ,  C25D5/02 ,  C25D5/04 ,  C25D7/12 ,  C25D17/00

    CPC classification number: H01L21/76831 ,  C23C18/1607 ,  C23C18/1651 ,  C23C18/1653 ,  C23C18/1669 ,  C23C18/1671 ,  H01L21/2885 ,  H01L21/76805 ,  H01L21/76843 ,  H01L21/76874 ,  H01L21/76879

    Abstract: A technique for utilizing an electric field to initiate electroless deposition of a material to form layers and/or structures on a semiconductor wafer. The wafer is disposed between a positive electrode and a negative electrode and disposed so that its deposition surface faces the positive electrode. A conductive surface on the wafer is then subjected to an electroless copper deposition solution. When copper is the conductive material being deposited, positive copper ions in the solution are repelled by the positive electrode and attracted by the negatively charged wafer surface. Once physical contact is made, the copper ions dissipate their charges by accepting electrons from the conductive surface, thereby forming copper atoms on the surface. The deposited copper have the catalytic properties so that when a reductant in the solution is absorbed at the copper sites and then oxidized, additional electrons are released into the conductive surface. The formation of the initial layer of copper functions as a seed layer for further electroless growth of copper. The same electroless deposition solution can be used for both the initial activation layer and the additional autocatalytic growth on to the seed layer.

    Abstract translation: 一种利用电场来引发化学沉积材料以在半导体晶片上形成层和/或结构的技术。 晶片设置在正电极和负电极之间并且被设置为使得其沉积表面面向正电极。 然后将晶片上的导电表面经受化学镀铜沉积溶液。 当铜是导电材料沉积时，溶液中的正铜离子被正极排斥并被带负电的晶片表面吸引。 一旦进行物理接触，铜离子通过从导电表面接受电子而耗散它们的电荷，从而在表面上形成铜原子。 沉积的铜具有催化性能，使得当溶液中的还原剂在铜位置被吸收然后被氧化时，附加的电子被释放到导电表面中。 铜的初始层的形成用作用于铜的进一步无电生长的种子层。 相同的无电沉积溶液可以用于初始活化层和在种子层上的额外的自催化生长。

Patent Agency Ranking