公开(公告)号：US09748369B2

公开(公告)日：2017-08-29

申请号：US15258412

申请日：2016-09-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: H01L29/735 ,  H01L29/66 ,  H01L21/285 ,  H01L29/08 ,  H01L29/45 ,  H01L29/423 ,  H01L29/73 ,  H01L29/10

CPC classification number: H01L29/735 ,  H01L21/28506 ,  H01L21/28518 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66257 ,  H01L29/7317

Abstract: A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in the semiconductor layer that is doped with a first conductivity type dopant at a first dopant concentration. The transistor emitter and collector are formed by regions doped with a second conductivity type dopant and located adjacent opposite sides of the base region. An extrinsic base includes an epitaxial semiconductor layer in contact with a top surface of the base region. The epitaxial semiconductor layer is doped with the first conductivity type dopant at a second dopant concentration greater than the first dopant concentration. Sidewall spacers on each side of the extrinsic base include an oxide liner on a side of the epitaxial semiconductor layer and the top surface of the base region.

公开(公告)号：US20170178967A1

公开(公告)日：2017-06-22

申请号：US15359953

申请日：2016-11-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc. ,  STMicroelectronics, Inc.

Inventor： Andrew M. Greene ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L21/8234 ,  H01L29/66 ,  H01L29/49 ,  H01L27/088

CPC classification number: H01L29/66545 ,  H01L21/76224 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/495 ,  H01L29/4966 ,  H01L29/4975 ,  H01L29/66515 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device that includes a first fin structure in a first portion of a substrate, and a second fin structure in a second portion of the substrate, wherein the first portion of the substrate is separated from the second portion of the substrate by at least one isolation region. A gate structure present extending from the first fin structure across the isolation region to the second fin structure. The gate structure including a first portion on the first fin structure including a first work function metal having at least one void, an isolation portion that is voidless present overlying the isolation region, and a second portion on the second fin structure including a second work function metal.

公开(公告)号：US09660083B2

公开(公告)日：2017-05-23

申请号：US14560255

申请日：2014-12-04

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation ,  GlobalFoundries Inc

Inventor： Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh ,  Xiuyu Cai

IPC: H01L29/78 ,  H01L29/08 ,  H01L29/417 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12

CPC classification number: H01L29/785 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/086 ,  H01L29/0869 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/41758 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7816 ,  H01L29/7835 ,  H01L29/7848

Abstract: A FinFET transistor includes a fin of semiconductor material with a transistor gate electrode extending over a channel region. Raised source and drain regions of first epitaxial growth material extending from the fin on either side of the transistor gate electrode. Source and drain contact openings extend through a pre-metallization dielectric material to reach the raised source and drain regions. Source and drain contact regions of second epitaxial growth material extend from the first epitaxial growth material at the bottom of the source and drain contact openings. A metal material fills the source and drain contact openings to form source and drain contacts, respectively, with the source and drain contact regions. The drain contact region may be offset from the transistor gate electrode by an offset distance sufficient to provide a laterally diffused metal oxide semiconductor (LDMOS) configuration within the raised source region of first epitaxial growth material.

公开(公告)号：US09633893B2

公开(公告)日：2017-04-25

申请号：US15081749

申请日：2016-03-25

Applicant: International Business Machines Corporation ,  STMicroelectronics, Inc.

Inventor： Nicolas Loubet ,  Qing Liu ,  Shom Ponoth

IPC: H01L21/76 ,  H01L21/762 ,  H01L21/84 ,  H01L21/311

CPC classification number: H01L21/76283 ,  H01L21/31111 ,  H01L21/76232 ,  H01L21/84

Abstract: Isolation trenches are etched through an active silicon layer overlying a buried oxide on a substrate into the substrate, and through any pad dielectric(s) on the active silicon layer. Lateral epitaxial growth of the active silicon layer forms protrusions into the isolation trenches to a lateral distance of at least about 5 nanometers, and portions of the isolation trenches around the protrusions are filled with dielectric. Raised source/drain regions are formed on portions of the active silicon layer including a dielectric. As a result, misaligned contacts passing around edges of the raised source/drain regions remain spaced apart from sidewalls of the substrate in the isolation trenches.

公开(公告)号：US09620507B2

公开(公告)日：2017-04-11

申请号：US13907460

申请日：2013-05-31

Applicant: STMicroelectronics, Inc. ,  International Business Machines Corporation

Inventor： Nicolas Loubet ,  Qing Liu ,  Prasanna Khare ,  Stephane Allegret-Maret ,  Bruce Doris ,  Kangguo Cheng

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L29/66772 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/092 ,  H01L27/1104 ,  H01L27/1116 ,  H01L29/78654

Abstract: An improved transistor with channel epitaxial silicon and methods for fabrication thereof. In one aspect, a method for fabricating a transistor includes: forming a gate stack structure on an epitaxial silicon region, a width dimension of the epitaxial silicon region approximating a width dimension of the gate stack structure; encapsulating the epitaxial silicon region under the gate stack structure with sacrificial spacers formed on both sides of the gate stack structure and the epitaxial silicon region; forming a channel of the transistor having a width dimension that approximates that of the epitaxial silicon region and the gate stack structure, the epitaxial silicon region and the gate stack structure formed on the channel of the transistor; removing the sacrificial spacers; and growing a raised epitaxial source and drain from the silicon substrate, with portions of the raised epitaxial source and drain in contact with the epitaxial silicon region.

公开(公告)号：US20170077306A1

公开(公告)日：2017-03-16

申请号：US15343021

申请日：2016-11-03

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing Liu ,  Xiuyu Cai ,  Chun-chen Yeh ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/266 ,  H01L21/28 ,  H01L29/423 ,  H01L29/417 ,  H01L21/265

CPC classification number: H01L29/7855 ,  H01L21/26513 ,  H01L21/266 ,  H01L21/28141 ,  H01L29/0653 ,  H01L29/0657 ,  H01L29/41783 ,  H01L29/42356 ,  H01L29/4236 ,  H01L29/51 ,  H01L29/518 ,  H01L29/66484 ,  H01L29/66787 ,  H01L29/66795 ,  H01L29/66818 ,  H01L29/7831 ,  H01L29/785

Abstract: A vertical slit transistor includes raised source, drain, and channel regions in a semiconductor substrate. Two gate electrodes are positioned adjacent respective sidewalls of the semiconductor substrate. A dielectric material separates the gate electrodes from the source and drain regions.

Abstract translation: 垂直狭缝晶体管包括半导体衬底中的凸起的源极，漏极和沟道区。 两个栅极位于半导体衬底的相应侧壁附近。 电介质材料将栅电极与源区和漏区分开。

公开(公告)号：US20170053982A1

公开(公告)日：2017-02-23

申请号：US15340491

申请日：2016-11-01

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Xiuyu Cai ,  Qing Liu ,  Ruilong Xie ,  Chun-Chen Yeh

IPC: H01L29/06 ,  H01L29/08 ,  H01L21/306 ,  H01L29/78 ,  H01L29/423 ,  H01L29/786 ,  H01L21/02 ,  H01L29/66 ,  H01L29/10 ,  H01L21/3065

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2029/7858

Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

Abstract translation: 实施例涉及制造纳米线场效应晶体管（FET）的一部分的方法。 该方法包括形成牺牲层和纳米线层，去除牺牲层的侧壁部分，并在牺牲层被去除的侧壁部分占据的空间中形成扩散块。 该方法还包括形成源极区域和漏极区域，使得扩散块在牺牲层与源区域和漏极区域中的至少一个之间，以及使用牺牲层去除工艺去除牺牲层，其中扩散 块防止牺牲层去除过程也去除源区和漏区中的至少一个的部分。

公开(公告)号：US09543436B2

公开(公告)日：2017-01-10

申请号：US14942566

申请日：2015-11-16

Applicant: STMICROELECTRONICS, INC. ,  STMICROELECTRONICS (CROLLES 2) SAS

Inventor： Qing Liu ,  Thomas Skotnicki

IPC: H01L29/10 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/78 ,  H01L21/28 ,  H01L27/12 ,  H01L29/423

CPC classification number: H01L29/7838 ,  H01L21/28114 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42356 ,  H01L29/66477 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66628 ,  H01L29/66651 ,  H01L29/7834

Abstract: An integrated circuit die includes a substrate having a first layer of semiconductor material, a layer of dielectric material on the first layer of semiconductor material, and a second layer of semiconductor material on the layer of dielectric material. An extended channel region of a transistor is positioned in the second layer of semiconductor material, interacting with a top surface, side surfaces, and potentially portions of a bottom surface of the second layer of semiconductor material. A gate dielectric is positioned on a top surface and on the exposed side surface of the second layer of semiconductor material. A gate electrode is positioned on the top surface and the exposed side surface of the second layer of semiconductor material.

Abstract translation: 集成电路管芯包括具有第一半导体材料层的衬底，第一半导体材料层上的介电材料层，以及介电材料层上的第二层半导体材料。 晶体管的扩展沟道区域位于第二半导体材料层中，与第二半导体材料层的顶表面，侧表面和潜在部分相互作用。 栅电介质位于第二层半导体材料的顶表面和暴露的侧表面上。 栅电极位于第二半导体材料层的顶表面和暴露的侧表面上。

公开(公告)号：US20160380087A1

公开(公告)日：2016-12-29

申请号：US15258412

申请日：2016-09-07

Applicant: STMicroelectronics, Inc.

Inventor： Qing Liu

IPC: H01L29/735 ,  H01L29/08 ,  H01L21/285 ,  H01L29/45 ,  H01L29/66

CPC classification number: H01L29/735 ,  H01L21/28506 ,  H01L21/28518 ,  H01L29/0804 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/42304 ,  H01L29/456 ,  H01L29/6625 ,  H01L29/66257 ,  H01L29/7317

Abstract: A bipolar transistor is supported by a substrate including a semiconductor layer overlying an insulating layer. A transistor base is formed by a base region in the semiconductor layer that is doped with a first conductivity type dopant at a first dopant concentration. The transistor emitter and collector are formed by regions doped with a second conductivity type dopant and located adjacent opposite sides of the base region. An extrinsic base includes an epitaxial semiconductor layer in contact with a top surface of the base region. The epitaxial semiconductor layer is doped with the first conductivity type dopant at a second dopant concentration greater than the first dopant concentration. Sidewall spacers on each side of the extrinsic base include an oxide liner on a side of the epitaxial semiconductor layer and the top surface of the base region.

Abstract translation: 双极晶体管由包括覆盖绝缘层的半导体层的衬底支撑。 晶体管基极由在第一掺杂浓度掺杂有第一导电型掺杂剂的半导体层中的基极区形成。 晶体管发射极和集电极由掺杂有第二导电型掺杂剂的区域形成，并且位于基极区域的相对侧。 外部基极包括与基极区域的顶表面接触的外延半导体层。 外延半导体层以大于第一掺杂剂浓度的第二掺杂剂浓度掺杂第一导电型掺杂剂。 外部基极的每一侧上的侧壁间隔物包括在外延半导体层的侧面上的氧化物衬垫和基极区域的顶表面。

公开(公告)号：US20160365411A1

公开(公告)日：2016-12-15

申请号：US14739543

申请日：2015-06-15

Applicant: International Business Machines Corporation ,  Globalfoundries, Inc. ,  STMicroelectronics, Inc.

Inventor： Chun-Chen Yeh ,  Xiuyu Cai ,  Qing Liu ,  Ruilong Xie

IPC: H01L29/06 ,  H01L21/265 ,  H01L29/78 ,  H01L21/3065 ,  H01L29/66

CPC classification number: H01L29/0673 ,  H01L21/02381 ,  H01L21/02532 ,  H01L21/30604 ,  H01L21/3065 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/42392 ,  H01L29/6656 ,  H01L29/66742 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78654 ,  H01L29/78696 ,  H01L2029/7858

Abstract: Embodiments are directed to a method of fabricating a portion of a nanowire field effect transistor (FET). The method includes forming a sacrificial layer and a nanowire layer, removing a sidewall portion of the sacrificial layer and forming a diffusion block in a space that was occupied by the removed sidewall portion of the sacrificial layer. The method further includes forming a source region and a drain region such that the diffusion block is between the sacrificial layer and at least one of the source region and the drain region, and removing the sacrificial layer using a sacrificial layer removal process, wherein the diffusion block prevents the sacrificial layer removal process from also removing portions of at least one of the source region and the drain region.

Abstract translation: 实施例涉及制造纳米线场效应晶体管（FET）的一部分的方法。 该方法包括形成牺牲层和纳米线层，去除牺牲层的侧壁部分，并在牺牲层被去除的侧壁部分占据的空间中形成扩散块。 该方法还包括形成源极区域和漏极区域，使得扩散块在牺牲层与源区域和漏极区域中的至少一个之间，以及使用牺牲层去除工艺去除牺牲层，其中扩散 块防止牺牲层去除过程也去除源区和漏区中的至少一个的部分。