公开(公告)号：US20090142885A1

公开(公告)日：2009-06-04

申请号：US11947858

申请日：2007-11-30

申请人： YA OU ,  Shom Ponoth ,  Hosadurga Shobha ,  Terry A. Spooner

发明人： YA OU ,  Shom Ponoth ,  Hosadurga Shobha ,  Terry A. Spooner

IPC分类号： H01L21/02

CPC分类号： H01L21/3105 ,  H01L21/76829 ,  H01L21/76832 ,  H01L21/76834

摘要： A method of forming a semiconductor structure chemically-mechanically polishes (CMP) a semiconductor structure before applying a sealant layer over the porous low-k dielectric. The process of applying the sealant layer is a selective process that causes the sealant to adhere to or deposit onto the porous low-k dielectric and to not adhere to the copper conductors. After the sealant layer is formed, the cap is applied. The parylene layer seals the pores in the low-k dielectric which prevents the low-k dielectric layer from being damaged during the cap pre-cleaning process and also prevents the cap material from penetrating into the low-k dielectric.

摘要翻译： 在多孔低k电介质上施加密封剂层之前，半导体结构的形成方法化学机械抛光（CMP）半导体结构。 施加密封剂层的过程是使密封剂粘附或沉积到多孔低k电介质上并且不粘附到铜导体的选择性过程。 在形成密封剂层之后，施加盖。 聚对二甲苯层密封低k电介质中的孔，防止低k电介质层在盖预清洁过程中受损，并且还防止盖材料渗入低k电介质。

公开(公告)号：US07498254B2

公开(公告)日：2009-03-03

申请号：US11682581

申请日：2007-03-06

申请人： Chih-Chao Yang ,  Simon Gaudet ,  Christian Lavoie ,  Shom Ponoth ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Simon Gaudet ,  Christian Lavoie ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L21/4763

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

摘要翻译： 提供一种互连结构，其包括具有增强的导电材料，优选Cu扩散性质的电镀种子层，其不需要使用单独的扩散和种子层。 具体地说，本发明提供了用于互连金属扩散增强的电镀种子层内的氧/氮过渡区域。 电镀种子层可以包括Ru，Ir或其合金，并且互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等。 优选地，互连导电材料是Cu或AlCu。 在更具体的术语中，本发明提供了单个接种层，其包括夹在顶部和底部种子区域之间的氧/氮过渡区域。 电镀种子层内的氧/氮过渡区的存在显着提高了电镀种子的扩散阻挡性。

公开(公告)号：US20070148826A1

公开(公告)日：2007-06-28

申请号：US11682581

申请日：2007-03-06

申请人： Chih-Chao Yang ,  Simon Gaudet ,  Christian Lavoie ,  Shom Ponoth ,  Terry Spooner

发明人： Chih-Chao Yang ,  Simon Gaudet ,  Christian Lavoie ,  Shom Ponoth ,  Terry Spooner

IPC分类号： H01L21/00

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

摘要翻译： 提供一种互连结构，其包括具有增强的导电材料，优选Cu扩散性质的电镀种子层，其不需要使用单独的扩散和种子层。 具体地说，本发明提供了用于互连金属扩散增强的电镀种子层内的氧/氮过渡区域。 电镀种子层可以包括Ru，Ir或其合金，并且互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等。 优选地，互连导电材料是Cu或AlCu。 在更具体的术语中，本发明提供了单个接种层，其包括夹在顶部和底部种子区域之间的氧/氮过渡区域。 电镀种子层内的氧/氮过渡区的存在显着提高了电镀种子的扩散阻挡性。

公开(公告)号：US07215006B2

公开(公告)日：2007-05-08

申请号：US11245540

申请日：2005-10-07

申请人： Chih-Chao Yang ,  Simon Gaudet ,  Christian Lavoie ,  Shom Ponoth ,  Terry A. Spooner

发明人： Chih-Chao Yang ,  Simon Gaudet ,  Christian Lavoie ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L23/58

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

摘要翻译： 提供一种互连结构，其包括具有增强的导电材料，优选Cu扩散性质的电镀种子层，其不需要使用单独的扩散和种子层。 具体地说，本发明提供了用于互连金属扩散增强的电镀种子层内的氧/氮过渡区域。 电镀种子层可以包括Ru，Ir或其合金，并且互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等。 优选地，互连导电材料是Cu或AlCu。 在更具体的术语中，本发明提供了单个接种层，其包括夹在顶部和底部种子区域之间的氧/氮过渡区域。 电镀种子层内的氧/氮过渡区的存在显着提高了电镀种子的扩散阻挡性。

公开(公告)号：US20070080429A1

公开(公告)日：2007-04-12

申请号：US11245540

申请日：2005-10-07

申请人： Chih-Chao Yang ,  Simon Gaudet ,  Christian Lavoie ,  Shom Ponoth ,  Terry Spooner

发明人： Chih-Chao Yang ,  Simon Gaudet ,  Christian Lavoie ,  Shom Ponoth ,  Terry Spooner

IPC分类号： H01L23/58

CPC分类号： H01L21/76843 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76856 ,  H01L21/76873 ,  H01L23/53238 ,  H01L2221/1089 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure which includes a plating seed layer that has enhanced conductive material, preferably, Cu, diffusion properties is provided that eliminates the need for utilizing separate diffusion and seed layers. Specifically, the present invention provides an oxygen/nitrogen transition region within a plating seed layer for interconnect metal diffusion enhancement. The plating seed layer may include Ru, Ir or alloys thereof, and the interconnect conductive material may include Cu, Al, AlCu, W, Ag, Au and the like. Preferably, the interconnect conductive material is Cu or AlCu. In more specific terms, the present invention provides a single seeding layer which includes an oxygen/nitrogen transition region sandwiched between top and bottom seed regions. The presence of the oxygen/nitrogen transition region within the plating seed layer dramatically enhances the diffusion barrier resistance of the plating seed.

摘要翻译： 提供一种互连结构，其包括具有增强的导电材料，优选Cu扩散性质的电镀种子层，其不需要使用单独的扩散和种子层。 具体地说，本发明提供了用于互连金属扩散增强的电镀种子层内的氧/氮过渡区域。 电镀种子层可以包括Ru，Ir或其合金，并且互连导电材料可以包括Cu，Al，AlCu，W，Ag，Au等。 优选地，互连导电材料是Cu或AlCu。 在更具体的术语中，本发明提供了单个接种层，其包括夹在顶部和底部种子区域之间的氧/氮过渡区域。 电镀种子层内的氧/氮过渡区的存在显着提高了电镀种子的扩散阻挡性。

公开(公告)号：US09620619B2

公开(公告)日：2017-04-11

申请号：US13348894

申请日：2012-01-12

申请人： Veeraraghavan S. Basker ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Veeraraghavan S. Basker ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/20 ,  H01L29/78 ,  H01L29/66 ,  H01L21/768 ,  H01L21/28

CPC分类号： H01L29/66545 ,  H01L21/76897 ,  H01L29/66628 ,  H01L29/78

摘要： A borderless contact structure or partially borderless contact structure and methods of manufacture are disclosed. The method includes forming a gate structure and a space within the gate structure, defined by spacers. The method further includes blanket depositing a sealing material in the space, over the gate structure and on a semiconductor material. The method further includes removing the sealing material from over the gate structure and on the semiconductor material, leaving the sealing material within the space. The method further includes forming an interlevel dielectric material over the gate structure. The method further includes patterning the interlevel dielectric material to form an opening exposing the semiconductor material and a portion of the gate structure. The method further includes forming a contact in the opening formed in the interlevel dielectric material.

公开(公告)号：US09059254B2

公开(公告)日：2015-06-16

申请号：US13604660

申请日：2012-09-06

申请人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

发明人： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/311

CPC分类号： H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

摘要： A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.

摘要翻译： 提供了一种方法，其包括首先根据第一掩模蚀刻衬底。 第一蚀刻在衬底中形成第一深度的第一蚀刻特征。 第一蚀刻还在衬底中形成条条开口。 然后可以用填充材料填充条子开口。 可以通过去除第一掩模的一部分来形成第二掩模。 可以用第二蚀刻蚀刻由第二掩模曝光的衬底，其中第二蚀刻对填充材料是选择性的。 第二蚀刻将第一蚀刻特征扩展到大于第一深度的第二深度，并且第二蚀刻形成第二蚀刻特征。 然后可以用导电金属填充第一蚀刻特征和第二蚀刻特征。

公开(公告)号：US09059243B2

公开(公告)日：2015-06-16

申请号：US13531654

申请日：2012-06-25

申请人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

发明人： Bruce B. Doris ,  Kangguo Cheng ,  Balasubramanian S. Haran ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Arvind Kumar ,  Shom Ponoth

IPC分类号： H01L21/70 ,  H01L21/762

CPC分类号： H01L29/0649 ,  H01L21/76224 ,  H01L21/76283

摘要： Shallow trench isolation structures are provided for use with UTBB (ultra-thin body and buried oxide) semiconductor substrates, which prevent defect mechanisms from occurring, such as the formation of electrical shorts between exposed portions of silicon layers on the sidewalls of shallow trench of a UTBB substrate, in instances when trench fill material of the shallow trench is subsequently etched away and recessed below an upper surface of the UTBB substrate.

摘要翻译： 提供了与UTBB（超薄体和掩埋氧化物）半导体衬底一起使用的浅沟槽隔离结构，其防止发生缺陷机制，例如在浅沟槽的侧壁上的硅层的暴露部分之间形成电短路 UTBB衬底，在浅沟槽的沟槽填充材料随后被蚀刻掉并凹入UTBB衬底的上表面的情况下。

公开(公告)号：US08772933B2

公开(公告)日：2014-07-08

申请号：US11954812

申请日：2007-12-12

申请人： Ya Ou ,  Shom Ponoth ,  Terry A. Spooner

发明人： Ya Ou ,  Shom Ponoth ,  Terry A. Spooner

IPC分类号： H01L23/48

CPC分类号： C23F4/00 ,  H01L21/76805 ,  H01L21/76829 ,  H01L21/76849 ,  H01L23/5226 ,  H01L23/53204 ,  H01L23/53238 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： An interconnect structure and method of fabricating the same is provided. More specifically, the interconnect structure is a defect free capped interconnect structure. The structure includes a conductive material formed in a trench of a planarized dielectric layer which is devoid of cap material. The structure further includes the cap material formed on the conductive material to prevent migration. The method of forming a structure includes selectively depositing a sacrificial material over a dielectric material and providing a metal capping layer over a conductive layer within a trench of the dielectric material. The method further includes removing the sacrificial material with any unwanted deposited or nucleated metal capping layer thereon.

摘要翻译： 提供了互连结构及其制造方法。 更具体地，互连结构是无缺陷的封装互连结构。 该结构包括形成在没有帽材料的平坦化介电层的沟槽中的导电材料。 该结构还包括形成在导电材料上以防止迁移的盖材料。 形成结构的方法包括在电介质材料上选择性地沉积牺牲材料，并在介电材料的沟槽内的导电层上提供金属覆盖层。 该方法还包括用其上的任何不需要的沉积或有核的金属覆盖层去除牺牲材料。

公开(公告)号：US08735279B2

公开(公告)日：2014-05-27

申请号：US13013108

申请日：2011-01-25

申请人： David V Horak ,  Elbert Huang ,  Charles W Koburger ,  Shom Ponoth ,  Chih-Chao Yang

发明人： David V Horak ,  Elbert Huang ,  Charles W Koburger ,  Shom Ponoth ,  Chih-Chao Yang

IPC分类号： H01L21/4763

CPC分类号： H01L23/522 ,  H01L21/76802 ,  H01L21/7682 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5222 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure is disclosed whereby multiple interconnect layers having effective air gaps positioned in regions most susceptible to capacitive coupling can be formed. The method includes providing a layer of conductive features, the layer including at least two line members disposed on a substrate and spaced from one another by less than or equal to an effective distance, and at least one such line member also having a via member extending away from the substrate, depositing a poorly conformal dielectric coating to form an air gap between such line members, and exposing a top end of the via.

摘要翻译： 公开了一种方法和结构，其中可以形成具有位于最容易受电容耦合的区域中的有效气隙的多个互连层。 该方法包括提供导电特征层，所述层包括设置在基底上并彼此隔开小于或等于有效距离的至少两个线构件，以及至少一个这样的线构件，其还具有延伸的通孔构件 离开基板，沉积不良共形介电涂层以在这些线构件之间形成气隙，并露出通孔的顶端。