公开(公告)号：US06919703B2

公开(公告)日：2005-07-19

申请号：US10459169

申请日：2003-06-11

Applicant: Eileen M. Marando ,  Robert W. Schoepflin ,  Richard E. Wahler

Inventor： Eileen M. Marando ,  Robert W. Schoepflin ,  Richard E. Wahler

IPC: G01P3/481 ,  G05B11/28

CPC classification number: G01P3/481

Abstract: A system may include a tachometer reading unit and a PWM (Pulse Width Modulated) signal generator configured to generate a PWM signal. The tachometer reading unit may be configured to obtain a tachometer reading from a tachometer signal generated by a device powered by the PWM signal. The tachometer reading unit includes a register configured to store a value indicative of a maximum stretching duration. The tachometer reading unit is configured to update the register in response to receiving a new value of the maximum stretching duration. The tachometer reading unit may be configured to control the PWM signal generator to stretch a pulse in the PWM signal and to not stretch the pulse longer than the maximum stretching duration indicated by the register. The tachometer reading unit is configured to obtain the tachometer reading during the stretched pulse in the PWM signal.

Abstract translation: 系统可以包括转速计读取单元和被配置为产生PWM信号的PWM（脉宽调制）信号发生器。 转速计读取单元可以被配置为从由PWM信号供电的装置产生的转速计信号获得转速计读数。 转速计读取单元包括配置为存储指示最大拉伸持续时间的值的寄存器。 转速计读取单元被配置为响应于接收到最大拉伸持续时间的新值而更新寄存器。 转速计读取单元可以被配置为控制PWM信号发生器在PWM信号中拉伸脉冲，并且不延伸比由寄存器指示的最大拉伸持续时间更长的脉冲。 转速计读数单元配置为在PWM信号中拉伸脉冲期间获得转速计读数。

公开(公告)号：US06856189B2

公开(公告)日：2005-02-15

申请号：US10447569

申请日：2003-05-29

Applicant: Thomas A. Somerville

Inventor： Thomas A. Somerville

IPC: G05F3/30 ,  G05F1/10

CPC classification number: G05F3/30

Abstract: A bandgap voltage reference generator may include a BJT (Bipolar Junction Transistor) and a pair of MOSFETs (Metal Oxide Semiconductor Field Effect Transistors) coupled to the BJT. The base-emitter voltage Vbe of the BJT may exhibit a non-linearity with respect to temperature. The difference between gate-source voltages of the pair of MOSFETs exhibits an opposite non-linearity with respect to temperature. The opposite non-linearity reduces the effect of the non-linearity on the output voltage of the bandgap voltage reference generator. The difference in gate-source voltages of the pair of MOSFETs may be determined by the ratio of channel width to channel length of each MOSFET included in the pair of MOSFETs.

Abstract translation: 带隙电压参考发生器可以包括耦合到BJT的BJT（双极结晶体管）和一对MOSFET（金属氧化物半导体场效应晶体管）。 BJT的基极 - 发射极电压Vbe可以表现出相对于温度的非线性。 一对MOSFET的栅源电压之间的差异表现出相对于温度的相反的非线性。 相反的非线性降低了非线性对带隙电压基准发生器的输出电压的影响。 一对MOSFET的栅极 - 源极电压的差可以由MOSFET对中包含的每个MOSFET的沟道宽度与沟道长度的比率来确定。

公开(公告)号：US5774009A

公开(公告)日：1998-06-30

申请号：US799253

申请日：1997-02-14

Applicant: Jay D. Popper

Inventor： Jay D. Popper

IPC: H03K5/1252 ,  H03K17/16

CPC classification number: H03K5/1252

Abstract: A clock generator circuit that produces clock signals at the logic signal transitions at an output in response to a sinewave input control signal derived from an oscillator includes a delay means connected in one of the inverter-amplifier stages to prevent unwanted noise-induced logic transitions at the output, thereby to reduce significantly the adverse effects of oscillator and power supply noise on the clock output signal.

Abstract translation: 响应于从振荡器导出的正弦波输入控制信号在输出处产生逻辑信号转变的时钟信号的时钟发生器电路包括连接在反相放大器级之一中的延迟装置，以防止不期望的噪声引起的逻辑转换 输出，从而显着降低振荡器和电源噪声对时钟输出信号的不利影响。

公开(公告)号：US5744990A

公开(公告)日：1998-04-28

申请号：US555369

申请日：1995-11-08

Applicant: Steven Burstein ,  Sharif M. Ibrahim

Inventor： Steven Burstein ,  Sharif M. Ibrahim

IPC: H03K17/22

CPC classification number: H03K17/223

Abstract: A comprehensive power-on-reset (POR) and low voltage detection circuit combines a Power Supply Voltage Level Detection (PSVLD) circuit with an Enhanced Retriggering (ER) circuit. The PSVLD circuit establishes lower and upper thresholds of the desired operating voltage range, and provide initial POR triggering and retriggering when the supply voltage is within the desired range. The ER circuit senses a predetermined amount of drop in the power supply voltage being monitored, and generates an independent pulse at the POR node whenever such a drop occurs. Total DC current is limited to less than 2.5 microamps, while power supply voltages can be monitored for stability over the range of 2.5 to 5.5 volts.

Abstract translation: 综合上电复位（POR）和低电压检测电路将电源电压电平检测（PSVLD）电路与增强型重触发（ER）电路相结合。 PSVLD电路建立所需工作电压范围的较低和较高阈值，并在电源电压在所需范围内时提供初始POR触发和重新触发。 ER电路检测到被监视的电源电压的预定量的下降，并且在发生这种下降时在POR节点处产生独立的脉冲。 总直流电流被限制在小于2.5微安，而电源电压可以在2.5至5.5伏的范围内监测稳定性。

公开(公告)号：US5708819A

公开(公告)日：1998-01-13

申请号：US541642

申请日：1995-10-10

Applicant: Jeffrey C. Dunnihoo

Inventor： Jeffrey C. Dunnihoo

IPC: G06F1/32 ,  G06F9/00

CPC classification number: G06F1/3203

Abstract: A process and apparatus for reducing power consumption in processor-based system by interrupting the main system power supply during periods of inactivity. Existing input/output circuitry is powered from a constant auxiliary power source to monitor system interrupts which are used to generate power events that control the on/off state of the main system power supply.

Abstract translation: 一种用于通过在不活动期间中断主系统电源来降低基于处理器的系统中的功耗的过程和装置。 现有的输入/输出电路由恒定的辅助电源供电，以监视用于产生控制主系统电源的开/关状态的电源事件的系统中断。

公开(公告)号：US5319260A

公开(公告)日：1994-06-07

申请号：US964490

申请日：1992-10-20

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H03K17/16

CPC classification number: H03K17/167

Abstract: A CMOS device having many output channels at least one of which channel includes a first pair of pull-up/pull-down of transistors between a "noisy Vcc and noisy ground", a second pair of pull-up/pull-down of transistors between a "quiet Vcc and quiet ground", and logic to switch the transistor pairs such that initial switching of an output is powered by the noisy Vcc and ground, and maintenance of an output state is powered by the quiet Vcc and ground. Quiescent channels are decoupled from active channels and will hold their assigned output levels.

Abstract translation: 具有许多输出通道的CMOS器件，其中至少一个通道包括在“噪声Vcc和噪声接地”之间的晶体管的第一对上拉/下拉，晶体管的第二对上拉/下拉 在“安静的Vcc和静音地”之间，以及切换晶体管对的逻辑，使得输出的初始切换由噪声Vcc和地面供电，并且输出状态的维持由静音Vcc和地面供电。 静态通道与有源通道分离，并保持其分配的输出电平。

公开(公告)号：US5313582A

公开(公告)日：1994-05-17

申请号：US693637

申请日：1991-04-30

Applicant: Ariel Hendel ,  Kenneth W. Brinkerhoff

Inventor： Ariel Hendel ,  Kenneth W. Brinkerhoff

IPC: G06F13/00 ,  G06F5/06 ,  G06F12/02 ,  H04L12/56 ,  H04L29/06

CPC classification number: H04L29/06 ,  G06F12/0223 ,  G06F5/06 ,  H04L49/90

Abstract: Method and apparatus are disclosed for buffering data packets in a data communication controller. The communication controller is interfaced with a host processor and includes a control unit for accessing a communication medium. Each data packet to be transmitted or received is assigned a packet number. Packet number assignment is carried out by a memory management unit within the communication controller which dynamically allocates to each assigned packet number one or more pages in a data packet buffer memory for the storage of the corresponding data packet. Upon issuing the assigned packet number, the physical addresses of the allocated pages of data packet buffer memory storage space are generated in a manner transparent to both the host processor and the control unit. Upon completion of each data packet loading operation, the corresponding packet number is stored in a packet number queue maintained for subsequent retrieval in order to generate the physical addresses at which the corresponding data packet has been stored. Also disclosed is a mechanism for automatically generating transmit interrupts to the host processor upon the completion of any preselected number of data packet transmissions determined by the host processor.

Abstract translation: 公开了用于在数据通信控制器中缓冲数据分组的方法和装置。 通信控制器与主处理器接口，并且包括用于访问通信介质的控制单元。 要发送或接收的每个数据包都被分配一个数据包号。 分组编号分配由通信控制器内的存储器管理单元执行，该存储器管理单元在数据分组缓冲存储器中动态地分配给每个分配的分组数量的一个或多个页面以存储对应的数据分组。 在发布分配的分组号时，以对主机处理器和控制单元两者都是透明的方式生成分配的数据分组缓冲存储器存储空间的页面的物理地址。 在完成每个数据分组加载操作时，相应的分组号被存储在保持为后续检索的分组号队列中，以便生成相应数据分组被存储的物理地址。 还公开了一种用于在完成由主机处理器确定的任何预选数量的数据分组传输的完成时自动产生到主处理器的传输中断的机制。

公开(公告)号：US5311083A

公开(公告)日：1994-05-10

申请号：US008669

申请日：1993-01-25

Applicant: Frank M. Wanlass

Inventor： Frank M. Wanlass

IPC: H03K19/0175 ,  G11C11/401 ,  H03K3/3565 ,  H03K17/0814 ,  H03K17/16 ,  H03K19/003 ,  H03K19/0185 ,  H03K9/0177

CPC classification number: H03K3/3565 ,  H03K17/08142 ,  H03K17/162 ,  H03K19/00315 ,  H03K19/00361 ,  H03K19/018521 ,  H03K19/018592

Abstract: A CMOS integrated circuit (IC) deviceembodiment of the present invention comprises an internal logic circuit operating with traditional 3.3 volt or five volt internal logic levels, an output buffer to convert the internal logic levels to external logic levels of 0.3 volts and an input buffer to convert the 0.3 volt external logic levels to the internal logic levels. In a CMOS IC device having numerous external output loads including relatively high capacitive values that are driven at very high clock rates, the restricted voltage swings of the 0.3 volt external logic levels permit unusually large numbers of devices to be driven without exceeding a predetermined power dissipation limit of the CMOS IC device. The low external logic levels further permit electrostatic discharge (ESD) protection to be included on all signal inputs and outputs of the CMOS IC device. The ESD protection comprises a pair of opposite polarity silicon PN junction diodes in parallel and connected between each signal line and a ground reference.

Abstract translation: 本发明的CMOS集成电路（IC）器件实施例包括一个内部逻辑电路，其工作于传统的3.3伏特或五伏内部逻辑电平，一个输出缓冲器将内部逻辑电平转换为0.3伏的外部逻辑电平，以及一个输入缓冲器 将0.3伏外部逻辑电平转换为内部逻辑电平。 在具有许多外部输出负载的CMOS IC器件中，包括以非常高的时钟速率驱动的相对较高的电容值，0.3伏外部逻辑电平的受限电压摆幅允许异常大量的器件被驱动而不超过预定的功耗 CMOS IC器件的极限。 低的外部逻辑电平进一步允许静电放电（ESD）保护被包括在CMOS IC器件的所有信号输入和输出端。 ESD保护包括并联的一对相反极性的硅PN结二极管，并且连接在每个信号线和接地基准之间。

公开(公告)号：US5170297A

公开(公告)日：1992-12-08

申请号：US553735

申请日：1990-07-13

Applicant: Richard Wahler ,  Carl Schooley ,  Robert Gross

Inventor： Richard Wahler ,  Carl Schooley ,  Robert Gross

IPC: G11B20/14 ,  H03L7/089 ,  H03L7/14 ,  H03L7/199 ,  H03M7/40 ,  H04L7/033

CPC classification number: H04L7/033 ,  G11B20/1403 ,  H03L7/0891 ,  H03L7/143 ,  H03L7/199

Abstract: A data separator for use in synchronizing data derived from a floppy disk or similar data source provides a variable net gain or loss of charge to vary the frequency of a voltage-controlled oscillator in accordance with the relative position of the data with respect to the clock until data centering or synchronization is achieved. The net charge is derived from a charge pump circuit that is controlled by a charge pump-up signal whose duration is proportional to the detected phase difference between the data and the clock, and a charge pump-down signal whose duration is one clock cycle. When the data pulse is centered within a clock cycle, the duration of a pump-up signal is one half that of a pump-down signal.

Abstract translation: 用于同步从软盘或类似数据源导出的数据的数据分离器提供可变的净增益或电荷损失，以根据数据相对于时钟的相对位置改变压控振荡器的频率 直到实现数据对中或同步。 净电荷来自电荷泵电路，该电荷泵电路由电荷泵浦信号控制，电荷泵浦信号的持续时间与检测到的数据和时钟之间的相位差成比例，以及持续时间为一个时钟周期的电荷泵浦信号。 当数据脉冲在时钟周期内居中时，泵浦信号的持续时间是抽水信号的一半。

公开(公告)号：US5125006A

公开(公告)日：1992-06-23

申请号：US447616

申请日：1989-12-08

Applicant: Frank Marinaro

Inventor： Frank Marinaro

IPC: H04L12/40

CPC classification number: H04L12/44 ,  H04L12/40013 ,  H04L12/40039 ,  H04L12/4625

Abstract: A transceiver for use in a local area network presents a high impedance to the cable when the transceiver is in its off state, that is, when it is not in the transmit mode. During the off state, the transformer that couples the transceiver to the cable is isolated from the transmitter section by reverse-biased diodes, which are forward biased when the transceiver is in the transmit or low-impedance mode.

Abstract translation: 当收发器处于关闭状态时，即不在发送模式时，用于局域网的收发器对电缆呈现高阻抗。 在关闭状态期间，将收发器耦合到电缆的变压器通过反向偏置二极管与发射机部分隔离，当收发器处于发送或低阻抗模式时，反向偏置二极管正向偏置。