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    SKEW DETECTOR AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME
    162.
    发明申请
    SKEW DETECTOR AND SEMICONDUCTOR MEMORY DEVICE USING THE SAME 有权
    使用它的SKEW检测器和半导体存储器件

    公开(公告)号：US20110158010A1

    公开(公告)日：2011-06-30

    申请号：US12648335

    申请日：2009-12-29

    Applicant: Seong-Jun LEE

    Inventor： Seong-Jun LEE

    IPC: G11C7/00 ,  G11C8/18 ,  H03K5/00

    CPC classification number: H03K19/00323 ,  G11C29/02 ,  G11C29/022 ,  G11C29/023 ,  G11C29/50012

    Abstract: A skew detection circuit includes a data sensing block configured to sense a first data that is transferred earliest and a last data that is transferred latest among a plurality of data which are transferred through different transfer paths, and generate a sensing result signal; and a detection signal generation block configured to compare an output signal of the data sensing block with a certain time, and generate a skew detection signal.

    Abstract translation: 歪斜检测电路包括：数据感测块，被配置为感测最早传送的第一数据;以及最后数据，其通过不同的传送路径传送的多个数据中最后传送，并产生感测结果信号; 以及检测信号生成块，被配置为将数据感测块的输出信号与一定时间进行比较，并生成偏斜检测信号。

    Method of estimating location of terminal in switched-beamforming based wireless communication system
    164.
    发明授权
    Method of estimating location of terminal in switched-beamforming based wireless communication system 有权
    基于交换波束成形的无线通信系统中终端位置的方法

    公开(公告)号：US07970356B2

    公开(公告)日：2011-06-28

    申请号：US11653199

    申请日：2007-01-12

    Applicant: Chang-Woo Seo ,  Jin-Youn Cho ,  Dong-Jun Lee ,  Kyung-Hun Jang ,  Gang-Youl Yu

    Inventor： Chang-Woo Seo ,  Jin-Youn Cho ,  Dong-Jun Lee ,  Kyung-Hun Jang ,  Gang-Youl Yu

    IPC: H04B15/00 ,  H04W24/00

    CPC classification number: H04W16/28 ,  H04W64/00

    Abstract: A terminal location estimation method in a wireless communication system in which an access point (AP) provides an access service to a plurality of terminals includes defining a plurality of beam spaces around the AP through space multiplexing; scheduling the beam spaces according to a predetermined pattern; simultaneously forming a beam in at least one beam space; and detecting the existence and location of a terminal according to whether a response message in response to the formed beam is received. Accordingly, an AP forms beams in a predetermined scheduling pattern, and each of the terminals detecting the beams registers its location by informing the AP that each of the terminals exists in a relevant beam area, and thus, a location of each of the terminals can be estimated without using a complex DOA algorithm.

    Abstract translation: 一种无线通信系统中的终端位置估计方法，其中接入点（AP）向多个终端提供接入服务包括通过空间多路复用来定义AP周围的多个波束空间; 根据预定模式调度光束空间; 同时在至少一个梁空间中形成梁; 以及根据是否接收到响应于所形成的波束的响应消息来检测终端的存在和位置。 因此，AP以预定的调度模式形成波束，并且通过向AP指示每个终端存在于相关的波束区域中，检测波束的每个终端登记其位置，因此每个终端的位置可以 估计不使用复杂的DOA算法。

    NITRIDE SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF
    167.
    发明申请
    NITRIDE SEMICONDUCTOR SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
    氮化物半导体基板及其制造方法

    公开(公告)号：US20110143525A1

    公开(公告)日：2011-06-16

    申请号：US13031425

    申请日：2011-02-21

    Applicant: Doo-Soo Kim ,  Ho-Jun Lee ,  Yong-Jin Kim ,  Dong-Kun Lee

    Inventor： Doo-Soo Kim ,  Ho-Jun Lee ,  Yong-Jin Kim ,  Dong-Kun Lee

    IPC: H01L21/365

    CPC classification number: H01L21/02658 ,  H01L21/0237 ,  H01L21/02381 ,  H01L21/02428 ,  H01L21/0254

    Abstract: The present invention relates to a nitride semiconductor substrate such as gallium nitride substrate and a method for manufacturing the same. The present invention forms a plurality of trenches on a lower surface of a base substrate that are configured to absorb or reduce stresses applied larger when growing a nitride semiconductor film on the base substrate from a central portion of the base substrate towards a peripheral portion. That is, the present invention forms the trenches on the lower surface of the base substrate such that pitches get smaller or widths or depths get larger from the central portion of the base substrate towards the peripheral portion.

    Abstract translation: 氮化镓半导体衬底及其制造方法技术领域本发明涉及氮化镓衬底等氮化物半导体衬底及其制造方法。 本发明在基底基板的下表面上形成多个沟槽，该多个沟槽被配置为当从基底基板的中心部朝向周边部分生长氮化物半导体膜时吸收或减小施加更大的应力。 也就是说，本发明在基底基板的下表面上形成沟槽，使得间距变得较小，或者宽度或深度从基底基板的中心部朝向周边部分变大。

    Semiconductor memory device capable of easily performing delay locking operation under high frequency system clock
    168.
    发明授权
    Semiconductor memory device capable of easily performing delay locking operation under high frequency system clock 有权
    半导体存储器件能够在高频系统时钟下容易地执行延迟锁定操作

    公开(公告)号：US07956659B2

    公开(公告)日：2011-06-07

    申请号：US11647645

    申请日：2006-12-29

    Applicant: Min-Young You ,  Seong-Jun Lee

    Inventor： Min-Young You ,  Seong-Jun Lee

    IPC: H03L7/00

    CPC classification number: H03L7/0812 ,  G06F1/04 ,  G11C7/22 ,  G11C7/222 ,  H03K5/1565

    Abstract: A semiconductor memory device includes a first clock buffer for outputting a first internal clock signal in response to an inverted signal of the system clock signal and for correcting a duty cycle ratio of the first internal clock signal in response to a control signal; a second clock buffer for outputting a second internal clock signal in response to the system clock signal and for correcting a duty cycle ratio of the second internal clock signal in response to the control signal; an analog duty cycle correction circuit for outputting the control signal corresponding to the duty cycle ratio of the first and second internal clock signals; a mixing circuit for mixing the first and second internal clock signals and for outputting a third internal clock signal whose duty cycle is corrected; and a DLL circuit for outputting a delay-locked clock signal by using the third internal clock signal.

    Abstract translation: 半导体存储器件包括：第一时钟缓冲器，用于响应于系统时钟信号的反相信号输出第一内部时钟信号，并用于响应于控制信号来校正第一内部时钟信号的占空比; 第二时钟缓冲器，用于响应于所述系统时钟信号输出第二内部时钟信号，并用于响应于所述控制信号来校正所述第二内部时钟信号的占空比; 模拟占空比校正电路，用于输出对应于第一和第二内部时钟信号的占空比的控制信号; 混合电路，用于混合第一和第二内部时钟信号，并输出其占空比被校正的第三内部时钟信号; 以及DLL电路，用于通过使用第三内部时钟信号输出延迟锁定时钟信号。

    Cooking apparatus
    169.
    发明授权
    Cooking apparatus 有权
    烹饪器具

    公开(公告)号：US07956309B2

    公开(公告)日：2011-06-07

    申请号：US11779589

    申请日：2007-07-18

    Applicant: Hyoung Jun Kim ,  Seung Jo Baek ,  Byeong Wook Park ,  Young Jun Lee

    Inventor： Hyoung Jun Kim ,  Seung Jo Baek ,  Byeong Wook Park ,  Young Jun Lee

    IPC: H05B3/68

    CPC classification number: H05B3/744 ,  F24C15/22

    Abstract: A burner for a glass top stove includes a heating element, and a reflector. The reflector is shaped to reflect heat and light emitted down and to the sides of the heater back up to the glass top of the burner. The reflector is shaped to form multiple images of the heater on the glass plate. This ensures uniform heating of the glass plate. It also causes a user to believe that there are more heaters than are actually mounted on the burner.

    Abstract translation: 玻璃顶炉的燃烧器包括加热元件和反射器。 反射器被成形为反射向下发射的热量和光，并将其加热到燃烧器的玻璃顶部。 反射器成形为在玻璃板上形成加热器的多个图像。 这确保玻璃板的均匀加热。 这也使得用户相信有比实际安装在燃烧器上更多的加热器。

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    170.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权
    半导体器件及其制造方法

    公开(公告)号：US20110121403A1

    公开(公告)日：2011-05-26

    申请号：US13014188

    申请日：2011-01-26

    Applicant: Seung-Jun LEE ,  Woonkyung Lee

    Inventor： Seung-Jun LEE ,  Woonkyung Lee

    IPC: H01L27/088

    CPC classification number: H01L21/36 ,  H01L21/02521 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11573 ,  H01L27/11578 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792 ,  H01L29/7926

    Abstract: A semiconductor device has a substrate that includes a cell array region and a dummy pattern region surrounding the cell array region. The cell array region includes a cell structure having a plurality of cell active pillars extending in a vertical direction from the cell array region of the substrate and includes cell gate patterns and cell gate interlayer insulating patterns alternately stacked on the substrate. The cell gate patterns and cell gate interlayer insulating patterns have sides facing the cell active pillars. The dummy pattern region includes a damp-proof structure.

    Abstract translation: 半导体器件具有包括单元阵列区域和围绕单元阵列区域的虚设图案区域的基板。 单元阵列区域包括具有从基板的单元阵列区域沿垂直方向延伸的多个单元有源柱的单元结构，并且包括交替层叠在基板上的单元栅极图案和单元栅极层间绝缘图案。 单元栅极图案和单元栅极层间绝缘图案具有面向单元活性柱的侧面。 虚设图案区域包括防潮结构。

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