公开(公告)号：US20190267922A1

公开(公告)日：2019-08-29

申请号：US16281604

申请日：2019-02-21

Applicant: STMicroelectronics (Grenoble 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Gwenael MAILLET ,  Jean-Louis LABYRE ,  Gilles BAS

IPC: H02P7/29 ,  G06K19/07 ,  G05B19/042

Abstract: Control over the operation of an electrically-controlled motor is supported by an interface circuit between the electrically-controlled motor and a near-field radio frequency communication controller. The interface circuit includes a first circuit that receives at least one control set point through a near-field radio frequency communication issued by the near-field radio frequency communication controller. A second circuit of the interface generates one or more electric signals in pulse width modulation based on the control set point.

公开(公告)号：US20190259942A1

公开(公告)日：2019-08-22

申请号：US16400649

申请日：2019-05-01

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Philippe BOIVIN

IPC: H01L45/00 ,  H01L27/24

Abstract: A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.

公开(公告)号：US20190245377A1

公开(公告)日：2019-08-08

申请号：US16267968

申请日：2019-02-05

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Laurent Truphemus ,  Sebastien Ortet

IPC: H02J9/00 ,  G06F1/26

CPC classification number: H02J9/005 ,  G06F1/263 ,  G06F1/30 ,  G11C5/14 ,  G11C5/141 ,  G11C11/40 ,  G11C11/4074 ,  G11C16/30

Abstract: An integrated circuit includes: a primary supply stage including a primary supply node, the primary supply stage being configured to deliver a primary supply voltage to the primary supply node; a secondary supply stage including a secondary supply node, the secondary supply stage being configured to deliver a secondary supply voltage to the secondary supply node; a supply-switching circuit; a pre-charging circuit controllably coupled to the secondary supply node via the supply-switching circuit; and a volatile memory circuit controllably coupled to the primary supply node and the secondary supply node via the supply-switching circuit, wherein the switching circuit is configured to connect a supply of the volatile memory circuit either to the primary supply node in a primary supply mode, or to the secondary supply node in a secondary supply mode.

公开(公告)号：US20190237589A1

公开(公告)日：2019-08-01

申请号：US16259424

申请日：2019-01-28

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Abderrezak MARZAKI

IPC: H01L29/94 ,  H01L29/66 ,  H01L27/06

CPC classification number: H01L29/945 ,  H01L27/0629 ,  H01L27/0733 ,  H01L29/66181

Abstract: A standard integrated cell includes a semiconductor region with a functional domain for logic circuits including a transistor and an adjacent continuity domain that extends out to an edge of the standard integrated cell. The edge is configured to be adjacent to another continuity domain of another standard integrated cell. The standard integrated cell further includes at capacitive element. This capacitive element may be housed in the continuity domain, for example at or near the edge. Alternatively, the capacitive element may be housed at a location which extends around a substrate region of the transistor.

公开(公告)号：US10347595B2

公开(公告)日：2019-07-09

申请号：US15609783

申请日：2017-05-31

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Clement Champeix ,  Nicolas Borrel

IPC: H03B1/00 ,  H03K5/00 ,  H01L23/00 ,  H01L25/065 ,  H01L23/48

Abstract: A device includes a first chip having a front side and a back side. A second chip is stacked with the first chip and located on the back side of the first chip. A first loop includes first and second through vias located in the first chip. Each through via has a first end on the front side of the first chip and a second end on the back side of the first chip. The first loop also includes a first track that connects the first ends of the first and second through vias is located in the first chip on the front side thereof and a second track that connects the second ends of the first and second through vias is located in the second chip. A detection circuit can detect an electrical characteristic of the first loop.

公开(公告)号：US10319906B2

公开(公告)日：2019-06-11

申请号：US15352985

申请日：2016-11-16

Applicant: STMICROELECTRONICS (ROUSSET) SAS

Inventor： Philippe Boivin

IPC: H01L27/24 ,  H01L45/00

Abstract: A oxide-based direct-access resistive nonvolatile memory may include within the interconnect portion of the integrated circuit a memory plane including capacitive memory cells extending in orthogonal first and second directions and each including a first electrode, a dielectric region and a second electrode. The memory plane may include conductive pads of square or rectangular shape forming the first electrodes. The stack of the dielectric layer and the second conductive layer covers the pads in the first direction and forms, in the second direction, conductive bands extending over and between the pads. The second electrodes may be formed by zones of the second bands facing the pads.

公开(公告)号：US10281512B2

公开(公告)日：2019-05-07

申请号：US15387370

申请日：2016-12-21

Applicant: STMicroelectronics S.r.l. ,  STMicroelectronics (Crolles 2) SAS ,  STMicroelectronics (Rousset) SAS

Inventor： Antonino Conte ,  Enrico Castaldo ,  Raul Andres Bianchi ,  Francesco La Rosa

IPC: G01R31/02 ,  G01R31/28 ,  G04F10/10

Abstract: A method can be used for testing a charge-retention circuit for measurement of a time interval having a storage capacitor coupled between a first biasing terminal and a floating node, and a discharge element coupled between the floating node and a reference terminal. The discharge element is configured to implement discharge of a charge stored in the storage capacitor by leakage through a corresponding dielectric. The method includes biasing the floating node at a reading voltage, detecting a biasing value of the reading voltage, implementing an operation of integration of the discharge current in the discharge element with the reading voltage kept constant at the biasing value, and determining an effective resistance value of the discharge element as a function of the operation of integration.

公开(公告)号：US20190123737A1

公开(公告)日：2019-04-25

申请号：US16161533

申请日：2018-10-16

Applicant: STMicroelectronics (Rousset) SAS

Inventor： Jimmy FORT ,  Nicolas BORREL ,  Francesco LA ROSA

IPC: H03K17/22 ,  G01R19/165 ,  H03K5/24 ,  G05F3/26 ,  G06F1/28

Abstract: A power supply voltage is monitored by a monitoring circuit including a variable current generator and a band gap voltage generator core receiving the variable current and including a first node and a second node. A control circuit connected to the first and second nodes is configured to deliver a control signal on a first output node having a first state when an increasing power supply voltage is below a first threshold and having a second state when increasing power supply voltage exceeds the first threshold. The first threshold is at least equal to the band gap voltage. An equalization circuit also connected to the first and second nodes with feedback to the variable current generator generates the bandgap voltage at a second output node. The control signal operates to control actuation of the equalization circuit.

公开(公告)号：US20190118544A1

公开(公告)日：2019-04-25

申请号：US16220476

申请日：2018-12-14

Applicant: STMicroelectronics (Rousset) SAS

Inventor： François Tailliet ,  Marc Battista ,  Victorien Brecte

IPC: B41J2/175

CPC classification number: B41J2/17556 ,  B41J2/175 ,  B41J2/17523 ,  B41J2/17596 ,  G11C7/067 ,  G11C16/0433 ,  G11C16/24 ,  G11C16/26

Abstract: A read amplifier of a memory device has two current generators, an inverter, and five transistors. The inverter is connected to the second current generator. The first transistor has a gate connected to the read amplifier, a drain connected to the first current generator, and a source connected to a reference ground. The second transistor has a gate connected to the first current generator, a drain connected to a reference voltage, and a source connected to the gate of the first transistor. The third transistor has a drain connected to the first current generator and a source connected to the reference ground. The fourth transistor has a gate connected to the first current generator, a drain connected to the second current generator, and a source connected to the reference ground. The fifth transistor has a drain connected to the second current generator and a source connected to the reference voltage.

公开(公告)号：US10271193B2

公开(公告)日：2019-04-23

申请号：US15905145

申请日：2018-02-26

Applicant: STMicroelectronics (Rousset) SAS ,  STMICROELECTRONICS GMBH

Inventor： Thierry Meziache ,  Pierre Rizzo ,  Alexandre Charles ,  Juergen Boehler

IPC: H04W88/06 ,  H04W4/80 ,  G06K7/00 ,  G06K7/10 ,  H04B5/00

Abstract: A device, including a main element (ME) and a set of at least two auxiliary elements (SEi), said main element including a master SWP interface (MINT), each auxiliary element including a slave SWP interface (SLINTi) connected to said master SWP interface of said NFC element through a controllably switchable SWP link (LK) and management means (PRM, CTLM, AMGi) configured to control said SWP link switching for selectively activating at once only one slave SWP interface on said SWP link.