公开(公告)号：US11204747B1

公开(公告)日：2021-12-21

申请号：US15786395

申请日：2017-10-17

Applicant: Xilinx, Inc.

Inventor： Jindrich Zejda ,  Elliott Delaye ,  Yongjun Wu ,  Aaron Ng ,  Ashish Sirasao ,  Khang K. Dao ,  Christopher J. Case

IPC: G06F9/45 ,  G06F8/41 ,  G06N3/02 ,  G06F13/28 ,  G06F8/30 ,  G06F9/451 ,  G06F9/50 ,  G06F13/362

Abstract: Embodiments herein describe techniques for interfacing a neural network application with a neural network accelerator that operate on two heterogeneous computing systems. For example, the neural network application may execute on a central processing unit (CPU) in a computing system while the neural network accelerator executes on a FPGA. As a result, when moving a software-hardware boundary between the two heterogeneous systems, changes may be made to both the neural network application (using software code) and to the accelerator (using RTL). The embodiments herein describe a software defined approach where shared interface code is used to express both sides of the interface between the two heterogeneous systems in a single abstraction (e.g., a software class).

公开(公告)号：US11204745B2

公开(公告)日：2021-12-21

申请号：US16420831

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Shail Aditya Gupta ,  Samuel R. Bayliss ,  Vinod K. Kathail ,  Ralph D. Wittig ,  Philip B. James-Roxby ,  Akella Sastry

IPC: G06F9/44 ,  G06F8/41 ,  G06F16/901 ,  G06F9/54 ,  G06F15/78

Abstract: Examples herein describe techniques for generating dataflow graphs using source code for defining kernels and communication links between those kernels. In one embodiment, the graph is formed using nodes (e.g., kernels) which are communicatively coupled by edges (e.g., the communication links between the kernels). A compiler converts the source code into a bit stream and/or binary code which configure a heterogeneous processing system of a SoC to execute the graph. The compiler uses the graph expressed in source code to determine where to assign the kernels in the heterogeneous processing system. Further, the compiler can select the specific communication techniques to establish the communication links between the kernels and whether synchronization should be used in a communication link. Thus, the programmer can express the dataflow graph at a high-level (using source code) without understanding about how the operator graph is implemented using the heterogeneous hardware in the SoC.

公开(公告)号：US11199581B1

公开(公告)日：2021-12-14

申请号：US16809399

申请日：2020-03-04

Applicant: Xilinx, Inc.

Inventor： John K. Jennings

IPC: G01R31/3177 ,  H03M1/06 ,  H03K19/17724 ,  G01R31/317 ,  H03M1/10

Abstract: Systems and methods for monitoring a number of operating conditions of a programmable device are disclosed. In some implementations, the system may include a root monitor including circuitry configured to generate a reference voltage, a plurality of sensors and satellite monitors distributed across the programmable device, and a network-on-chip (NoC) interconnect system coupled to the root monitor and to each of the plurality of satellite monitors. Each of the satellite monitors may be in a vicinity of and coupled to a corresponding one of the plurality of sensors via a local interconnect.

公开(公告)号：US20210367353A1

公开(公告)日：2021-11-25

申请号：US17257137

申请日：2019-07-24

Applicant: XILINX, INC.

Inventor： Peter MEYER

IPC: H01Q21/00 ,  H01Q21/28 ,  H01Q3/24 ,  H01Q3/30

Abstract: The present invention provides an antenna module for a massive MIMO antenna, the antenna module comprising a plurality of first signal ports, a number of first antenna elements arranged in a first matrix arrangement, wherein a number of rows of the first matrix arrangement and/or a number of columns of the first matrix arrangement equals the number of first signal ports, and a switching matrix that is configured to controllably couple each of the first signal ports either with all first antenna elements of a respective row of the first matrix arrangement or all first antenna elements of a respective column of the first matrix arrangement. Further, the present invention provides a respective massive MIMO antenna.

公开(公告)号：US11182110B1

公开(公告)日：2021-11-23

申请号：US16547550

申请日：2019-08-21

Applicant: Xilinx, Inc.

Inventor： Ahmad R. Ansari ,  Sagheer Ahmad

IPC: G06F3/06 ,  H03K19/17728 ,  G11C5/14 ,  G11C7/22 ,  G11C11/4076 ,  G06F5/06 ,  G06F13/16 ,  G06F1/3206 ,  G11C7/24 ,  H03K19/173

Abstract: A memory block circuit can include a plurality of data interfaces, a switch connected to each data interface of the plurality of data interfaces, and a plurality of memory banks each coupled to the switch. Each memory bank can include a memory controller and a random access memory connected to the memory controller. The memory block circuit also includes a control interface and a management controller connected to the control interface and each memory bank of the plurality of memory banks. Each memory bank can be independently controlled by the management controller.

公开(公告)号：US11177795B1

公开(公告)日：2021-11-16

申请号：US16855962

申请日：2020-04-22

Applicant: XILINX, INC.

Inventor： Jun Liu ,  Bruce Young

IPC: H03K3/037

Abstract: A master latch includes a latch input node and a latch output node, a first inverter with an input and an output, the input coupled to the latch input node and the output coupled to the latch output node, and a second inverter with an input and an output, the input coupled to the latch output node and the output coupled to the latch input node. The master latch further includes a first pull-up device connected between a source voltage and the latch input node, the first pull-up device configured to pull the latch input node up towards the source voltage when the latch output node is low, and a first pull-down device connected between the latch input node and a ground voltage, the first pull-down device configured to pull the latch input node towards the ground voltage when the latch output node is high.

公开(公告)号：US11169892B1

公开(公告)日：2021-11-09

申请号：US17169067

申请日：2021-02-05

Applicant: XILINX, INC.

Inventor： Sarosh Azad ,  Akshay Shetty ,  Alex Warshofsky

IPC: G06F11/16

Abstract: Embodiments herein describe a hardware solution where a reset monitor in an integrated circuit detects and reports unintentional resets. A glitch in a reset path can cause a logic block to initiate an undesired or unintentional reset. As a result, the local circuitry in the logic block resets which causes them to lose data and their current state. In the embodiments herein, the reset monitor can monitor the reset signals generated within the logic blocks in the circuit. The reset monitor can compare these reset signals to golden copies of the resets signals generated by the reset generator. If a reset signal generated within a logic block does not match the corresponding golden copy of the reset signal, the reset monitor determines that an unintentional reset has occurred.

公开(公告)号：US11163605B1

公开(公告)日：2021-11-02

申请号：US16571776

申请日：2019-09-16

Applicant: XILINX, INC.

Inventor： Sonal Santan ,  Min Ma ,  Soren Soe ,  Cheng Zhen ,  Lizhi Hou ,  Yu Liu

IPC: G06F9/46 ,  G06F9/48

Abstract: Examples herein describe techniques for launching and executing a pipeline formed by heterogeneous processing units. A system on a chip (SoC) can include different hardware elements which form a collection of heterogeneous processing units, such as general purpose processor, programmable logic array, and specialized processors. These processing units are heterogeneous meaning their underlying hardware and techniques for processing data are different, in contrast to a system that using homogeneous processing units. In the embodiments herein, the heterogeneous processing units can be arranged into a pipeline where each stage of the pipeline is performed by one of the processing units.

公开(公告)号：US11144235B1

公开(公告)日：2021-10-12

申请号：US16534527

申请日：2019-08-07

Applicant: Xilinx, Inc.

Inventor： Rowan Lyons ,  Noel Brady

IPC: G06F3/06 ,  G06F11/26

Abstract: Disclosed approaches for measuring memory performance include inputting respective sets of parameter values for master circuits. Each set specifies control over a transaction issuance rate, a transaction size, or an address pattern. Configuration data is generated for implementing master circuits in programmable logic circuitry based on the sets of parameter values. Each master circuit is configured to issue memory transactions according to the respective set of parameter values. The programmable logic circuitry is configured with the configuration data, and the master circuits are activated. Each master circuit issues memory transactions based on the respective set of parameter values. Each master circuit measures performance metrics of memory circuitry in processing the memory transactions and stores data indicative of the performance metrics.

公开(公告)号：US11138019B1

公开(公告)日：2021-10-05

申请号：US16420935

申请日：2019-05-23

Applicant: Xilinx, Inc.

Inventor： Akella Sastry ,  Henri Fraisse ,  Rishi Surendran ,  Abnikant Singh

IPC: G06F9/445 ,  G06F13/40 ,  G06F16/901 ,  G06F13/28

Abstract: An example method of implementing an application for a system-on-chip (SOC) having a data processing engine (DPE) array including determining a graph representation of the application, the graph representation including nodes representing kernels of the application and edges representing communication between the kernels, mapping, based on the graph, the kernels onto DPEs of the DPE array and data structures of the kernels onto memory in the DPE array, building a routing graph of all possible routing choices in the DPE array for communicate channels between DPEs and circuitry of the application configured in programmable logic of the SOC, adding constraints to the routing graph based on an architecture of the DPE array, routing communication channels between DPEs and circuitry of the application configured in programmable logic of the SOC based on the routing graph, and generating implementation data for programming the SOC to implement the application based on results of the mapping and the routing.