Abstract:
A field effect transistor including a dielectric layer on a substrate, a nano-structure material (NSM) layer on the dielectric layer, a source electrode and a drain electrode formed on the NSM layer, a gate dielectric formed on at least a portion of the NSM layer between the source electrode and the drain electrode, a T-shaped gate electrode formed between the source electrode and the drain electrode, where the NSM layer forms a channel of the FET, and a doping layer on the NSM layer extending at least from the sidewall of the source electrode to a first sidewall of the gate dielectric, and from a sidewall of the drain electrode to a second sidewall of the gate dielectric.
Abstract:
A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode.
Abstract:
A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode.
Abstract:
A method of fabricating a semiconductor device includes depositing a dielectric layer on a substrate and a nanomaterial on the dielectric layer. The method also includes depositing a thin metal layer on the nanomaterial and removing a portion of the thin metal layer from a gate area. The method also includes depositing a gate dielectric layer. The method also includes selectively removing the gate dielectric layer from a source contact region and a drain contact region. The method also includes patterning a gate electrode, a source electrode, and a drain electrode.
Abstract:
Structures and methods that include selective electrostatic placement based on a dipole-to-dipole interaction of electron-rich carbon nanotubes onto an electron-deficient pre-patterned surface. The structure includes a substrate with a first surface having a first isoelectric point and at least one additional surface having a second isoelectric point. A self-assembled monolayer is selectively formed on the first surface and includes an electron deficient compound including a deprotonated pendant hydroxamic acid or a pendant phosphonic acid group or a pendant catechol group bound to the first surface. An organic solvent can be used to deposit the electron rich carbon nanotubes on the self-assembled monolayer.
Abstract:
Carbon-based light emitting diodes (LEDs) and techniques for the fabrication thereof are provided. In one aspect, a LED is provided. The LED includes a substrate; an insulator layer on the substrate; a first bottom gate and a second bottom gate embedded in the insulator layer; a gate dielectric on the first bottom gate and the second bottom gate; a carbon material on the gate dielectric over the first bottom gate and the second bottom gate, wherein the carbon material serves as a channel region of the LED; and metal source and drain contacts to the carbon material.
Abstract:
Techniques for use of carbon nanotubes as an anti-tampering feature and for use of randomly metallic or semiconducting carbon nanotubes in the generation of a physically unclonable cryptographic key generation are provided. In one aspect, a cryptographic key having an anti-tampering feature is provided which includes: an array of memory bits oriented along at least one bit line and at least one word line, wherein each of the memory bits comprises a memory cell, wherein the cryptographic key is stored in the memory cell, and wherein the memory cell is connected to the at least one bit line; and a metallic carbon nanotube interconnect which connects the memory cell to the at least one word line. A cryptographic key and method for processing the cryptographic key are also provided.
Abstract:
A field effect transistor includes a substrate and a gate dielectric formed on the substrate. A channel material is formed on the dielectric layer. The channel material includes carbon nanotubes. A patterned resist layer has openings formed therein. Metal contacts are formed on the channel material in the openings in the patterned resist layer and over portions of the patterned resist layer to protect sidewalls of the metal contacts to prevent degradation of the metal contacts.
Abstract:
Embodiments relate to the authentication of a semiconductor. An identification circuit disposed within a package of an integrated circuit, and the identification circuit includes carbon-nanotube transistors configured to generate an encryption key.
Abstract:
Embodiments relate to the authentication of a semiconductor. An identification circuit disposed within a package of an integrated circuit, and the identification circuit includes carbon-nanotube transistors configured to generate an encryption key.