公开(公告)号：US11238945B1

公开(公告)日：2022-02-01

申请号：US17006197

申请日：2020-08-28

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C7/00 ,  G11C16/34 ,  G11C16/30 ,  G11C16/26 ,  G11C16/10

Abstract: Methods, systems, and devices that support techniques for programming self-selecting memory are described. Received data may include a first group of bits that each have a first logic value and a second group of bits that each have a second logic value. The first and second group of bits may be stored in a first set of memory cells and a second set of memory cells, respectively. A first programming operation for writing the second logic value to both the first and second set of memory cells and verifying whether the second logic value is written to each of the first set of memory cells, the second set of memory cells, or both may be performed. A second programming operation may write the first logic value to either the first set of memory cells or the second set of memory cells based on a result of the verification.

公开(公告)号：US11238907B2

公开(公告)日：2022-02-01

申请号：US16512999

申请日：2019-07-16

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/12 ,  G11C11/22

Abstract: Methods and devices for techniques for precharging a memory cell are described. Precharging a memory cell while the memory cell is coupled with its digit line may reduce a total duration of an access operation thereby reducing a latency associated with accessing a memory device. During a read operation, the memory device may select a word line to couple the memory cell with a selected digit line. Further, the memory device may selectively couple the selected digit line with a reference digit line that is to be precharged to a given voltage. A difference in voltage between the selected digit line and the reference digit line at the completion of precharging may represent a signal indicative of a logic state of the memory cell. The memory device may use a capacitor precharged to a first voltage to capture the signal. In some cases, the memory device may continue to perform a self-reference operation using the same memory cell, the selected digit line, and the reference digit line to produce a reference signal using the capacitor precharged to a different voltage. A similar precharging steps may be repeated during the self-reference operation. The selected word line may remain activated during the read operation and the self-reference operation.

公开(公告)号：US20220020448A1

公开(公告)日：2022-01-20

申请号：US17387335

申请日：2021-07-28

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo ,  Riccardo Muzzetto

IPC: G11C29/42 ,  G11C29/44 ,  G11C5/02 ,  G11C11/4074 ,  G11C11/4091 ,  G11C29/02

Abstract: Methods, systems, and devices for method for setting a reference voltage for read operations are described. A memory device may perform a first read operation on a set of memory cells using a first reference voltage and detect a first codeword based on performing the first read operation using the first reference voltage. The memory device may compare a first quantity of bits of the first codeword having a first logic value (e.g., a logic value ‘1’) with an expected quantity of bits having the first logic value (e.g., the expected quantity of logic value ‘1’s stored by the set of memory cells). The memory device may determine whether to perform a second read operation on the set of memory cells using a second reference voltage different than the first reference voltage (e.g., greater or less than the first reference voltage) based on the comparing.

公开(公告)号：US11049540B2

公开(公告)日：2021-06-29

申请号：US16703754

申请日：2019-12-04

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22 ,  G11C11/56 ,  G11C11/00

Abstract: Techniques, systems, and devices for time-resolved access of memory cells in a memory array are described herein. During a sense portion of a read operation, a selected memory cell may be charged to a predetermined voltage level. A logic state stored on the selected memory cell may be identified based on a duration between the beginning of the charging and when selected memory cell reaches the predetermined voltage level. In some examples, time-varying signals may be used to indicate the logic state based on the duration of the charging. In some examples, the duration of the charging may be based on a polarization state of the selected memory cell, a dielectric charge state of the selected state, or both a polarization state and a dielectric charge state of the selected memory cell.

公开(公告)号：US20200098413A1

公开(公告)日：2020-03-26

申请号：US16592630

申请日：2019-10-03

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C11/22 ,  G11C11/4091 ,  G11C7/06 ,  G11C5/14 ,  G11C11/404 ,  G11C11/409 ,  G11C11/408 ,  G11C7/10

Abstract: Methods, systems, and devices for operating a memory cell or cells are described. A capacitor coupled with an access line may be precharged and then boosted such that the charge stored in the capacitor is elevated to a higher voltage with respect to a memory cell. The boosted charge in the capacitor may support sensing operations that would otherwise require a relatively higher voltage. Some embodiments may employ charge amplification between an access line and a sense component, which may amplify signals between the memory cell and the sense component, and reduce charge sharing between these components. Some embodiments may employ “sample-and-hold” operations, which may re-use certain components of a sense component to separately generate a signal and a reference, reducing sensitivity to manufacturing and/or operational tolerances. In some embodiments, sensing may be further improved by employing “self-reference” operations that use a memory cell to generate its own reference.

公开(公告)号：US10529410B2

公开(公告)日：2020-01-07

申请号：US15845619

申请日：2017-12-18

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Lucia Di Martino

IPC: G11C11/4091 ,  G11C11/4074

Abstract: Techniques are described herein for mitigating parasitic signals induced by state transitions during an access operation of a selected memory cell in a memory device. Some memory devices may include a plate that is coupled with memory cells associated with a plurality of digit lines and/or a plurality of word lines. Because the plate is coupled with a plurality of digit lines and/or word lines, unintended coupling between various components of the memory device may occur during an access operation. To mitigate parasitic signals induced by the unintended coupling, the memory device may isolate the selected memory cell from a selected digit line during certain portions of the access operation. The memory device may isolate the selected memory cell when the plate transitions from a first voltage to a second, when the selected digit line transitions from a third voltage to a fourth voltage, or a combination thereof.

公开(公告)号：US20190333563A1

公开(公告)日：2019-10-31

申请号：US15962941

申请日：2018-04-25

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo

IPC: G11C11/22

Abstract: Devices and methods for sensing a memory cell are described. The memory cell may include a ferroelectric memory cell. During a read operation, a cascode may couple a precharged capacitor with the memory cell to transfer a charge between the precharged capacitor and the memory cell. The cascode may isolate the capacitor from the memory cell based on the charge transferred between the capacitor and the memory cell. A second capacitor (e.g., a parasitic capacitor) may continue to provide an additional amount of charge to the memory cell during the read operation. Such a change in capacitance value during the read operation may provide a large sense window due to a non-linear voltage characteristics associated with the change in capacitance value.

公开(公告)号：US10446232B2

公开(公告)日：2019-10-15

申请号：US15846373

申请日：2017-12-19

Applicant: Micron Technology, Inc.

Inventor： Umberto Di Vincenzo ,  Riccardo Muzzetto ,  Ferdinando Bedeschi

IPC: G11C11/22 ,  G11C14/00

Abstract: The present provision includes apparatuses, methods, and systems for charge separation for memory sensing. An embodiment includes applying a sensing voltage to a memory cell, and determining a data state of the memory cell based, at least in part, on a comparison of an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell before a particular reference time and an amount of charge discharged by the memory cell while the sensing voltage is being applied to the memory cell after the particular reference time.

公开(公告)号：US20190130955A1

公开(公告)日：2019-05-02

申请号：US16184480

申请日：2018-11-08

Applicant: Micron Technology, Inc.

Inventor： Daniele Vimercati ,  Scott James Derner ,  Umberto Di Vincenzo ,  Christopher Johnson Kawamura ,  Eric S. Carman

IPC: G11C11/22

Abstract: Methods, systems, and devices for operating a ferroelectric memory cell or cells are described. A ground reference scheme may be employed in a digit line voltage sensing operation. A positive voltage may be applied to a memory cell; and after a voltage of the digit line of the cell has reached a threshold, a negative voltage may be applied to cause the digit line voltages to center around ground before a read operation. In another example, a first voltage may be applied to a memory cell and then a second voltage that is equal to an inverse of the first voltage may be applied to a reference capacitor that is in electronic communication with a digit line of the memory cell to cause the digit line voltages to center around ground before a read operation.

公开(公告)号：US20190035441A1

公开(公告)日：2019-01-31

申请号：US16020834

申请日：2018-06-27

Applicant: Micron Technology, Inc.

Inventor： Ferdinando Bedeschi ,  Umberto Di Vincenzo

IPC: G11C7/14 ,  G11C11/24 ,  G11C11/22 ,  G11C11/408

CPC classification number: G11C7/14 ,  G11C5/063 ,  G11C5/147 ,  G11C8/08 ,  G11C8/14 ,  G11C11/221 ,  G11C11/2253 ,  G11C11/2297 ,  G11C11/24 ,  G11C11/408

Abstract: Methods, systems, and devices for variable filter capacitance are described. Within a memory device, voltages may be applied to access lines associated with two voltage sources to increase the capacitance provided by the access lines between the two voltage sources. In some cases, the access lines may be in electronic communication with capacitive cells that include a capacitive element and a selection component, and the voltage sources and access lines may be configured to utilize the capacitive elements and the capacitance between the access lines to generate an increase capacitance between the voltage sources. In some cases, decoders may be used to implement certain configurations that generate different capacitance levels. Similarly, sub-decoders may generate different capacitance levels by selecting portions of a capacitive array.