公开(公告)号：US20220005823A1

公开(公告)日：2022-01-06

申请号：US16918392

申请日：2020-07-01

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/11565

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. The stack comprises laterally-spaced memory-block regions. Channel-material strings extend through the first tiers and the second tiers. Material of the first tiers is of different composition from material of the second tiers. Conducting material is formed in one of the first tiers. The conducting material comprises a seam in and longitudinally-along opposing sides of individual of the memory-block regions in the one first tier. The seam is penetrated with a fluid that forms intermediate material in the seam longitudinally-along the opposing sides of the individual memory-block regions in the one first tier and comprises a different composition from that of the conducting material. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20210384216A1

公开(公告)日：2021-12-09

申请号：US16891297

申请日：2020-06-03

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  John D. Hopkins

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/11519 ,  H01L27/1157 ,  H01L27/11565 ,  H01L21/3215

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a conductor tier comprising conductor material on a substrate. Laterally-spaced memory-block regions are formed and individually comprise a vertical stack comprising alternating first tiers and second tiers directly above the conductor tier. Channel-material strings of memory cells extend through the first tiers and the second tiers. Horizontally-elongated lines are formed in the conductor material between the laterally-spaced memory-block regions. The horizontally-elongated lines are of different composition from an upper portion of the conductor material that is laterally-between the horizontally-elongated lines. After the horizontally-elongated lines are formed, conductive material of a lowest of the first tiers is formed that directly electrically couples together the channel material of individual of the channel-material strings and the conductor material of the conductor tier. Other embodiments, including structure independent of method, are disclosed.

公开(公告)号：US20210313346A1

公开(公告)日：2021-10-07

申请号：US17347587

申请日：2021-06-15

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Purnima Narayanan ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L23/522 ,  H01L21/768 ,  H01L21/3215 ,  H01L21/311

Abstract: Some embodiments include a method of forming an integrated assembly. A stack of alternating first and second materials is formed over a conductive structure. The conductive structure includes a semiconductor-containing material over a metal-containing material. An opening is formed to extend through the stack and through the semiconductor-containing material, to expose the metal-containing material. The semiconductor-containing material is doped with carbon and/or with one or more metals. After the doping of the semiconductor-containing material, the second material of the stack is removed to form voids. Conductive material is formed within the voids. Insulative material is formed within the opening. Some embodiments include integrated assemblies having carbon distributed within at least a portion of a semiconductor material.

公开(公告)号：US20210233933A1

公开(公告)日：2021-07-29

申请号：US17230541

申请日：2021-04-14

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Shyam Surthi ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L29/49 ,  H01L29/51 ,  H01L21/28 ,  H01L29/792 ,  H01L29/788 ,  H01L21/02 ,  H01L27/11556

Abstract: Some embodiments include a NAND memory array having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include terminal regions, and include nonterminal regions proximate the terminal regions. The terminal regions are vertically thicker than the nonterminal regions, and are configured as segments which are vertically stacked one atop another and which are vertically spaced from one another. Blocks are adjacent to the segments and have approximately a same vertical thickness as the segments. The blocks include high-k dielectric material, charge-blocking material and charge-storage material. Channel material extends vertically along the stack and is adjacent to the blocks. Some embodiments include integrated assemblies. Some embodiments include methods of forming integrated assemblies.

公开(公告)号：US20210167020A1

公开(公告)日：2021-06-03

申请号：US16702222

申请日：2019-12-03

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Lifang Xu ,  Rita J. Klein ,  Xiao Li ,  Everett A. McTeer

IPC: H01L23/532 ,  H01L23/522 ,  H01L23/00 ,  H01L21/768

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

公开(公告)号：US20210111064A1

公开(公告)日：2021-04-15

申请号：US16599856

申请日：2019-10-11

Applicant: Micron Technology, Inc.

Inventor： Daniel Billingsley ,  Jordan D. Greenlee ,  Yongjun Jeff Hu

IPC: H01L21/762 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: A method used in forming a memory array comprising strings of memory cells comprises forming a stack comprising vertically-alternating first tiers and second tiers. Horizontally-elongated trenches are formed into the stack to form laterally-spaced memory-block regions. Bridge material is formed across the trenches laterally-between and longitudinally-along immediately-laterally-adjacent of the memory-block regions. The bridge material comprises longitudinally-alternating first and second regions. The first regions of the bridge material are ion implanted differently than the second regions of the bridge material to change relative etch rate of one of the first or second regions relative to the other in an etching process. The first and second regions are subjected to the etching process to selectively etch away one of the first and second regions relative to the other to form bridges that extend across the trenches laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory-block regions. Other embodiments and structure independent of method are disclosed.

公开(公告)号：US20210098486A1

公开(公告)日：2021-04-01

申请号：US16585418

申请日：2019-09-27

Applicant: Micron Technology, Inc.

Inventor： John D. Hopkins ,  Jordan D. Greenlee

IPC: H01L27/11582 ,  H01L23/528 ,  H01L27/11556 ,  H01L23/532 ,  H01L21/02 ,  H01L21/311 ,  H01L21/28 ,  H01L27/11565 ,  H01L27/11519

Abstract: Some embodiments include a memory device having a vertical stack of alternating insulative levels and conductive levels. The conductive levels include first regions, and include second regions laterally adjacent to the first regions. The first regions have a first vertical thickness and at least two different metal-containing materials along the first vertical thickness. The second regions have a second vertical thickness at least as large as the first vertical thickness, and have only a single metal-containing material along the second vertical thickness. Dielectric-barrier material is laterally adjacent to the first regions. Charge-blocking material is laterally adjacent to the dielectric-barrier material. Charge-storage material is laterally adjacent to the charge-blocking material. Dielectric material is laterally adjacent to the charge storage material. Channel material is laterally adjacent to the dielectric material.

公开(公告)号：US10943921B2

公开(公告)日：2021-03-09

申请号：US16751116

申请日：2020-01-23

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Chet E. Carter ,  Collin Howder ,  John Mark Meldrim ,  Everett A. McTeer

IPC: H01L27/11582 ,  H01L21/3213 ,  H01L29/10 ,  H01L21/768 ,  H01L23/532 ,  H01L21/285 ,  H01L23/528 ,  H01L27/11556 ,  H01L21/28 ,  H01L29/49 ,  H01L27/11519 ,  H01L27/11565

Abstract: Some embodiments include a method of forming an integrated structure. An assembly is formed to include a stack of alternating first and second levels. The first levels have insulative material, and the second levels have voids which extend horizontally. The assembly includes channel material structures extending through the stack. A first metal-containing material is deposited within the voids to partially fill the voids. The deposited first metal-containing material is etched to remove some of the first metal-containing material from within the partially-filled voids. Second metal-containing material is then deposited to fill the voids.

公开(公告)号：US20200350333A1

公开(公告)日：2020-11-05

申请号：US16933693

申请日：2020-07-20

Applicant: Micron Technology, Inc.

Inventor： Liu Liu ,  David Daycock ,  Rithu K. Bhonsle ,  Giovanni Mazzone ,  Narula Bilik ,  Jordan D. Greenlee ,  Minsoo Lee ,  Benben Li

IPC: H01L27/11582 ,  H01L27/11524 ,  H01L21/32 ,  H01L27/1157 ,  H01L21/311 ,  H01L27/11556

Abstract: Some embodiments include a method of forming stacked memory decks. A first deck has first memory cells arranged in first tiers disposed one atop another, and has a first channel-material pillar extending through the first tiers. An inter-deck structure is over the first deck. The inter-deck structure includes an insulative expanse, and a region extending through the insulative expanse and directly over the first channel-material pillar. The region includes an etch-stop structure. A second deck is formed over the inter-deck structure. The second deck has second memory cells arranged in second tiers disposed one atop another. An opening is formed to extend through the second tiers and to the etch-stop structure. The opening is subsequently extended through the etch-stop structure. A second channel-material pillar is formed within the opening and is coupled to the first channel-material pillar. Some embodiments include integrated assemblies.

公开(公告)号：US20200328284A1

公开(公告)日：2020-10-15

申请号：US16383862

申请日：2019-04-15

Applicant: Micron Technology, Inc.

Inventor： Jordan D. Greenlee ,  Rita J. Klein ,  Everett A. McTeer ,  John Mark Meldrim

IPC: H01L29/49 ,  H01L27/11556 ,  H01L27/11582

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and wordline levels. Channel material extends vertically along the stack. The wordline levels include conductive regions which have a first metal-containing material and a second metal-containing material. The first metal-containing material at least partially surrounds the second metal-containing material. The first metal-containing material has a different crystallinity than the second metal-containing material. In some embodiments the first metal-containing material is substantially amorphous, and the second metal-containing material has a mean grain size within a range of from greater than or equal to about 5 nm to less than or equal to about 200 nm. Charge-storage regions are adjacent the wordline levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.