公开(公告)号：US20080135877A1

公开(公告)日：2008-06-12

申请号：US11568404

申请日：2005-04-11

Applicant: Akira Inoue ,  Haruyuki Sorada ,  Yoshio Kawashima ,  Takeshi Takagi

Inventor： Akira Inoue ,  Haruyuki Sorada ,  Yoshio Kawashima ,  Takeshi Takagi

IPC: H01L21/8234 ,  H01L27/088

CPC classification number: H01L21/02381 ,  H01L21/02532 ,  H01L21/02639 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823481 ,  H01L27/0207 ,  H01L27/088

Abstract: A production method for a semiconductor device according to the present invention includes: step (A) of providing a substrate including a semiconductor layer having a principal face, the substrate having a device isolation structure (STI) formed in an isolation region 70 for partitioning the principal face into a plurality of device active regions 50, 60; step (B) of growing an epitaxial layer containing Si and Ge on selected device active regions 50 among the plurality of device active regions 50, 60 of the principal face of the semiconductor layer; and step (C) of forming a transistor in, among the plurality of device active regions 50, 60, each of the device active regions 50 on which the epitaxial layer is formed and each of the device active regions A2 on which the epitaxial layer is not formed. Step (A) includes step (a1) of forming, in the isolation region 70, a plurality of dummy regions 80 surrounded by the device isolation structure (STI), and step (B) includes step (b1) of growing a layer of the same material as that of the epitaxial layer on selected regions among the plurality of dummy regions 80.

Abstract translation: 根据本发明的半导体器件的制造方法包括：步骤（A），其提供包括具有主面的半导体层的衬底，所述衬底具有形成在隔离区域70中的器件隔离结构（STI），用于分割 主面进入多个设备有源区域50,60; 在半导体层的主面的多个器件有源区50,60中的选定器件有源区50上生长含有Si和Ge的外延层的工序（B） 以及在多个器件有源区域50,60中形成晶体管的步骤（C），在其上形成有外延层的器件有源区域50中的每个器件有源区域A 2上，其上的外延层 没有形成。 步骤（A）包括在隔离区域70中形成被器件隔离结构（STI）包围的多个虚拟区域80的步骤（a1），步骤（B）包括步骤（b1） 与多个虚拟区域80中的选定区域上的外延层相同的材料。

公开(公告)号：US20080118942A1

公开(公告)日：2008-05-22

申请号：US11666055

申请日：2005-10-25

Applicant: Koji Sugiyama ,  Takeshi Takagi

Inventor： Koji Sugiyama ,  Takeshi Takagi

IPC: C12Q1/20 ,  C12M1/34

CPC classification number: G01N27/3271

Abstract: The present invention relates to a method for measuring the concentration of a particular component in a blood sample containing blood cells based on a variable correlated with the concentration of the particular component. In the present invention, a concentration (S) in blood plasma obtained by removing blood cell components from the blood sample, a concentration (DI) in the blood sample computed by a differential method and a concentration (EP) in the blood sample computed by an equilibrium point method are expressed by a relational expression which is unrelated to the proportion of the blood cell components in the blood sample, and the concentration of the particular component is computed by using the relational expression.

Abstract translation: 本发明涉及基于与特定成分的浓度相关的变量来测定含有血细胞的血液样品中特定成分的浓度的方法。 在本发明中，通过从血液样品中除去血细胞成分而获得的血浆中的浓度（S），通过微分法计算的血液样品中的浓度（DI）和血液样品中的浓度（EP） 平衡点法由与血样中血细胞成分比例无关的关系表达式表示，特定成分的浓度用关系式计算。

公开(公告)号：US07126170B2

公开(公告)日：2006-10-24

申请号：US10978513

申请日：2004-11-02

Applicant: Akira Inoue ,  Takeshi Takagi ,  Akira Asai ,  Haruyuki Sorada

Inventor： Akira Inoue ,  Takeshi Takagi ,  Akira Asai ,  Haruyuki Sorada

IPC: H01L31/0336

CPC classification number: H01L21/28123 ,  H01L29/1054 ,  H01L29/1087 ,  H01L29/4238 ,  H01L29/66651 ,  H01L29/783

Abstract: A MISFET according to this invention includes: a substrate having a semiconductor layer; an active region formed in the semiconductor layer; a gate insulator formed on the active region; a gate formed on the gate insulator; and a source region and a drain region, wherein: the active region is formed, in plan view, to have a body portion and a projecting portion projecting from a periphery of the body portion; the gate is formed, in plan view, to intersect the body portion of the active region, cover a pair of connecting portions connecting a periphery of the projecting portion to the periphery of the body portion and allow a part of the projecting portion to project from a periphery of the gate; and the source region and the drain region are formed in regions of the body portion of the active region which are situated on opposite sides of the gate in plan view, respectively.

Abstract translation: 根据本发明的MISFET包括：具有半导体层的衬底; 形成在半导体层中的有源区; 形成在有源区上的栅极绝缘体; 形成在栅极绝缘体上的栅极; 源极区域和漏极区域，其中：有源区域在平面图中形成为具有从主体部分的周边突出的主体部分和突出部分; 在平面图中，门形成为与有源区域的主体部分相交，覆盖将突出部分的周边连接到主体部分的周边的一对连接部分，并使突出部分的一部分从 门的周边; 并且源极区域和漏极区域分别形成在有源区域的主体部分的位于平面图的栅极的相对侧上的区域中。

公开(公告)号：US20060208300A1

公开(公告)日：2006-09-21

申请号：US10549291

申请日：2004-03-19

Applicant: Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

Inventor： Junko Iwanaga ,  Takeshi Takagi ,  Yoshihiko Kanzawa ,  Haruyuki Sorada ,  Tohru Saitoh ,  Takahiro Kawashima

IPC: H01L27/108

CPC classification number: H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66795

Abstract: A semiconductor device includes: a semiconductor substrate in which a trench is formed; a source region and a drain region each of which is buried in the trench and contains an impurity of the same conductive type; a semiconductor FIN buried in the trench and provided between the source and drain regions; a gate insulating film provided on a side surface of the semiconductor FIN as well as the upper surface of the semiconductor FIN; and a gate electrode formed on the gate insulating film.

Abstract translation: 一种半导体器件包括：形成沟槽的半导体衬底; 源极区域和漏极区域，每个源极区域和漏极区域被埋在沟槽中并且包含相同导电类型的杂质; 掩埋在沟槽中并设置在源区和漏区之间的半导体FIN; 设置在半导体FIN的侧表面上的栅极绝缘膜以及半导体FIN的上表面; 以及形成在栅极绝缘膜上的栅电极。

公开(公告)号：US07084484B2

公开(公告)日：2006-08-01

申请号：US10910573

申请日：2004-08-04

Applicant: Akira Asai ,  Takeshi Takagi

Inventor： Akira Asai ,  Takeshi Takagi

IPC: H01L27/082

CPC classification number: H01L29/66242 ,  H01L21/8222 ,  H01L27/0823 ,  H01L27/0826 ,  H01L29/7378

Abstract: A semiconductor integrated circuit including a plurality of bipolar transistors that are produced by forming, in a plurality of transistor-producing regions, a first conductive type emitter layer on the front surface side of a second conductive type base layer that is formed on the surface side of a first conductive collector layer and contains germanium, the first conductive type emitter layer being formed from a semiconductor material having a band gap larger than the base layer. The concentrations of impurities contained in the emitter layers vary among the plurality of transistor-producing regions, and the germanium concentrations differ in the base-emitter junction interfaces of at least two of the transistor-producing regions, such that the ON-state voltages required for turning the plurality of bipolar transistors into an ON state differ from each other. This semiconductor integrated circuit makes it possible to reduce power consumption while maintaining the excellent performance of a bipolar transistor.

Abstract translation: 一种半导体集成电路，包括多个双极晶体管，其通过在多个晶体管产生区域中形成在表面侧形成的第二导电型基极层的前表面侧的第一导电型发射极层 的第一导电集电极层并且包含锗，所述第一导电型发射极层由具有大于所述基极层的带隙的半导体材料形成。 包含在发射极层中的杂质的浓度在多个晶体管产生区域之间变化，并且锗浓度在至少两个晶体管产生区域的基极 - 发射极结界面中不同，使得需要ON状态电压 用于将多个双极晶体管转换成导通状态彼此不同。 该半导体集成电路使得可以在保持双极晶体管的优异性能的同时降低功耗。

公开(公告)号：US06987065B2

公开(公告)日：2006-01-17

申请号：US10891038

申请日：2004-07-15

Applicant: Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

Inventor： Haruyuki Sorada ,  Takeshi Takagi ,  Akira Asai ,  Akira Inoue

IPC: H01L21/311

CPC classification number: H01L29/78696 ,  H01L21/76264 ,  H01L21/76281 ,  H01L29/1054 ,  H01L29/66742 ,  H01L29/78687 ,  Y10S438/933 ,  Y10S438/938

Abstract: The present invention provides a semiconductor device comprising: a semiconductor layer (3); a gate electrode (11) formed on the semiconductor layer (3) via a gate insulation film (10); and a first insulation film (13) formed at one or more of sidewalls of the semiconductor layer (3), the gate insulation film (10) and the gate electrode (11); wherein the first insulation film (13) overlies a part of the gate insulation film (10) surface. According to the semiconductor device, leakage current at the isolation edge can be suppressed and thus reliability can be improved.

Abstract translation: 本发明提供一种半导体器件，包括：半导体层（3）; 经由栅极绝缘膜（10）形成在所述半导体层（3）上的栅电极（11）; 以及形成在所述半导体层（3），所述栅极绝缘膜（10）和所述栅电极（11）的侧壁的一个或多个的第一绝缘膜（13）。 其中所述第一绝缘膜（13）覆盖所述栅极绝缘膜（10）表面的一部分。 根据半导体装置，可以抑制隔离边缘处的漏电流，从而可以提高可靠性。

公开(公告)号：US06939772B2

公开(公告)日：2005-09-06

申请号：US10882220

申请日：2004-07-02

Applicant: Akira Asai ,  Teruhito Ohnishi ,  Takeshi Takagi

Inventor： Akira Asai ,  Teruhito Ohnishi ,  Takeshi Takagi

IPC: H01L29/73 ,  H01L21/331 ,  H01L29/10 ,  H01L29/165 ,  H01L29/36 ,  H01L29/737 ,  H07L21/8249 ,  H07L21/331

CPC classification number: H01L29/66242 ,  H01L29/1004 ,  H01L29/36 ,  H01L29/7378 ,  Y10S438/936

Abstract: A SiGe spacer layer 151, a graded SiGe base layer 152 including boron, and an Si-cap layer 153 are sequentially grown through epitaxial growth over a collector layer 102 on an Si substrate. A second deposited oxide film 112 having a base opening portion 118 and a P+ polysilicon layer 115 that will be made into an emitter connecting electrode filling the base opening portion are formed on the Si-cap layer 153, and an emitter diffusion layer 153a is formed by diffusing phosphorus into the Si-cap layer 153. When the Si-cap layer 153 is grown, by allowing the Si-cap layer 153 to include boron only at the upper part thereof by in-situ doping, the width of a depletion layer 154 is narrowed and a recombination current is reduced, thereby making it possible to improve the linearity of the current characteristics.

Abstract translation: 通过在Si衬底上的集电极层102上的外延生长，顺序地生长SiGe间隔层151，包括硼的梯度SiGe基极层152和Si覆盖层153。 在Si覆盖层153上形成有第二沉积氧化物膜112，其具有基底开口部分118和将形成填充基部开口部分的发射极连接电极的P +多晶硅层115，发射极扩散层153a 通过将磷扩散到Si覆盖层153中而形成。当Si覆盖层153生长时，通过使Si覆盖层153仅通过原位掺杂在其上部包含硼而形成， 层154变窄，复合电流降低，从而可以提高电流特性的线性。

公开(公告)号：US06909506B2

公开(公告)日：2005-06-21

申请号：US10347842

申请日：2003-01-16

Applicant: Takeshi Takagi ,  Kazuhiro Ikeda ,  Tatsuya Hatano ,  Hiroshi Matsuura

Inventor： Takeshi Takagi ,  Kazuhiro Ikeda ,  Tatsuya Hatano ,  Hiroshi Matsuura

IPC: G01J4/00

CPC classification number: G01J4/00

Abstract: An object is to accurately measure the Stokes parameters, without the occurrence of polarization fluctuations or PDL during the splitting of the incident light. When the incident light is made incident on a first-stage prism, the light is split into two first splitting light rays. Next, the first split light rays are respectively incident on a pair of prisms of a second stage. Each of the pair of first split light rays is split into two rays by a second-stage prism, to obtain four second split light rays.

Abstract translation: 目的是精确测量斯托克斯参数，而不会在入射光分裂期间出现极化波动或PDL。 当入射光入射在第一级棱镜上时，光被分成两个第一分裂光线。 接下来，第一分裂光线分别入射到第二级的一对棱镜上。 一对第一分裂光线中的每一个被第二级棱镜分成两束，以获得四条第二分裂光线。

公开(公告)号：US20050031371A1

公开(公告)日：2005-02-10

申请号：US10902790

申请日：2004-08-02

Applicant: Miho Kaida ,  Takeshi Takagi

Inventor： Miho Kaida ,  Takeshi Takagi

IPC: G03G21/00 ,  G03G7/00 ,  G03G21/16 ,  H04N1/00 ,  G03G15/00

CPC classification number: G03G7/00 ,  G03G7/0053 ,  G03G21/1628 ,  G03G2215/00548 ,  G03G2221/1687

Abstract: The invention provides an image forming apparatus including an image forming portion for forming an image, an image reading portion for reading an image, displaceable with respect to the image forming portion, and an open/closable member that can be opened or closed with respect to a main body of the image forming portion and displaced toward the image reading portion, wherein the displacement of the open/closable member is effected in relation to the displacement of the image reading portion. In this manner the open/closable member can be opened or closed by a simple operation, without increasing the dimension of the image forming apparatus.

Abstract translation: 本发明提供了一种图像形成装置，包括用于形成图像的图像形成部分，用于读取图像的图像读取部分，可相对于图像形成部分移位;以及打开/关闭部件，其可相对于 图像形成部分的主体并朝向图像读取部分移动，其中打开/关闭部件的位移相对于图像读取部分的位移进行。 以这种方式，可以通过简单的操作来打开或关闭打开/关闭构件，而不增加图像形成装置的尺寸。

公开(公告)号：US06800532B2

公开(公告)日：2004-10-05

申请号：US10620613

申请日：2003-07-17

Applicant: Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

Inventor： Teruhito Ohnishi ,  Takeshi Takagi ,  Akira Asai ,  Taizo Fujii ,  Mitsuo Sugiura ,  Yoshihisa Minami

IPC: H01L218222

CPC classification number: H01L29/93 ,  H01L27/0664 ,  H01L27/0808

Abstract: A variable capacitor includes an N+ layer including a variable capacitance region, a P+ layer epitaxially grown on the N+ layer and formed from a SiGe film and a Si film, and a P-type electrode. An NPN-HBT (Hetero-junction Bipolar Transistor) includes a collector diffusion layer formed simultaneously with the N+ layer of the variable capacitor, a collector layer, and a Si/SiGe layer epitaxially grown simultaneously with the P+ layer of the variable capacitor. Since a depletion layer formed in a PN junction of the variable capacitor can extend entirely across the N+ layer, reduction in variation range of the capacitance can be suppressed.

Abstract translation: 可变电容器包括N +层，包括可变电容区，在N +层上外延生长并由SiGe膜和Si膜形成的P +层和P型电极。 NPN-HBT（异质结双极晶体管）包括与可变电容器的N +层同时形成的集电极扩散层，集电极层和与P +层同时外延生长的Si / SiGe层 的可变电容器。 由于形成在可变电容器的PN结中的耗尽层可以完全延伸穿过N +层，所以可以抑制电容的变化范围的减小。