公开(公告)号：US4879526A

公开(公告)日：1989-11-07

申请号：US246111

申请日：1988-09-19

Applicant: Edoardo Botti ,  Aldo Torazzina

Inventor： Edoardo Botti ,  Aldo Torazzina

IPC: H03F3/68 ,  H03F3/72

CPC classification number: H03F3/72 ,  H03F3/68

Abstract: A monolithically integrated audio amplifier which is commutable from a stereo configuration to a bridge configuration and vice versa may have only seven pins, namely: two output pins, two input pins, an supply pin, a ground pin and a SVR pin. It comprises two operational amplifiers which may both have two distinct input differential stages, a first input differential stage being fedback according to a stereo configuration while the other input differential stage being fedback according to a bridge configuration of the two operational amplifiers. A comparator with an internally fixed threshold determines, in function of its output state, the switching on or the switching off of one or the other of said two distinct input differential stages of the two operational amplifiers and, therefore, either a stereo configuration or a bridge configuration of the audio amplifier. The input terminal of the comparator may be connected to an input pin or to the SVR pin of the amplifier and a biasing DC voltage level may be imposed thereto through external biasing means for selecting the desired configuration.

公开(公告)号：US06154163A

公开(公告)日：2000-11-28

申请号：US108080

申请日：1998-06-29

Applicant: Annamaria Rossi ,  Giona Fucili ,  Marcello Leone ,  Maurizio Nessi

Inventor： Annamaria Rossi ,  Giona Fucili ,  Marcello Leone ,  Maurizio Nessi

IPC: H03M1/46 ,  H03M1/38

CPC classification number: H03M1/462

Abstract: A successive approximation register has a serial input and output comprises a chain of logic circuits of the bistable type which have selectable input terminals feedback connected by a storage and control element and logic gate circuits of the OR-type, and connected to a serial line through respective internal switches communicating the serial line to input terminals of the logic circuits in said chain, the serial line forming an input to a flip-flop of the D type which is the output element of the register.

Abstract translation: 逐次逼近寄存器具有串行输入和输出，其包括双稳态类型的逻辑电路链，其具有通过存储和控制元件反馈连接的可选输入端和OR型逻辑门电路，并连接到串行线 各个内部开关将串行线路传送到所述链路中的逻辑电路的输入端，该串行线路形成作为寄存器的输出元件的D型触发器的输入。

公开(公告)号：US6127723A

公开(公告)日：2000-10-03

申请号：US16073

申请日：1998-01-30

Applicant: Natale Aiello ,  Atanasio La Barbera ,  Stefano Sueri ,  Sergio Spampinato

Inventor： Natale Aiello ,  Atanasio La Barbera ,  Stefano Sueri ,  Sergio Spampinato

IPC: H01L27/06 ,  H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC classification number: H01L27/0635

Abstract: An integrated device in an emitter-switching configuration comprises a first bipolar transistor having a base region, an emitter region, and a collector region, a second transistor having a charge-collection terminal connected to an emitter terminal of the first transistor, and a quenching element having a terminal connected to a base terminal of the first transistor. The quenching element is formed within the base region or the emitter region of the first transistor.

Abstract translation: 发射极切换配置中的集成器件包括具有基极区域，发射极区域和集电极区域的第一双极晶体管，具有连接到第一晶体管的发射极端子的电荷收集端子的第二晶体管，以及淬火 元件具有连接到第一晶体管的基极端子的端子。 淬灭元件形成在第一晶体管的基极区域或发射极区域内。

公开(公告)号：US6122702A

公开(公告)日：2000-09-19

申请号：US951261

申请日：1997-10-16

Applicant: Sergio Pelagalli ,  Marco Olivo

Inventor： Sergio Pelagalli ,  Marco Olivo

IPC: G11C11/41 ,  G06F12/02 ,  G11C8/00 ,  H01L21/8242 ,  H01L27/108 ,  G06F12/00 ,  G11C11/00

CPC classification number: G11C8/00 ,  G06F12/02

Abstract: The invention relates to a matrix of memory cells for a semiconductor integrated microcontroller. The matrix is of the type intended for accommodation between macrocells of the microcontroller so as to reduce the needed circuit area on the semiconductor. The matrix comprises memory cells which are organized into rows and columns, with the number of columns defining the matrix height. The matrix height is advantageously variable according to the number of bits intended for selecting the matrix column, while its width is dependent on the overall capacity of the memory.

Abstract translation: 本发明涉及用于半导体集成微控制器的存储器单元矩阵。 矩阵是用于在微控制器的宏单元之间调节的类型，以便减少半导体上所需的电路面积。 矩阵包括被组织成行和列的存储单元，列数定义矩阵高度。 矩阵高度有利地根据用于选择矩阵列的位数可变，而其宽度取决于存储器的总体容量。

公开(公告)号：US06114746A

公开(公告)日：2000-09-05

申请号：US686753

申请日：1996-07-26

Applicant: Salvatore Leonardi ,  Pietro Lizzio ,  Davide Giuseppe Patti ,  Sergio Palara

Inventor： Salvatore Leonardi ,  Pietro Lizzio ,  Davide Giuseppe Patti ,  Sergio Palara

IPC: H01L21/331 ,  H01L29/10 ,  H01L29/732 ,  H01L27/082

CPC classification number: H01L29/66272 ,  H01L29/1004 ,  H01L29/7322

Abstract: A vertical PNP transistor integrated in a semiconductor material wafer having an N type substrate and an N type epitaxial layer forming a surface. The transistor has a P type buried collector region astride the substrate and the epitaxial layer; a collector sinker insulating an epitaxial tub from the rest of the wafer; a gain-modulating N type buried base region astride the buried collector region and the epitaxial tub, and forming a base region with the epitaxial tub; and a P type emitter region in the epitaxial tub. An N.sup.+ type base sinker extends from the surface, through the epitaxial tub to the buried base region. The gain of the transistor may be modulated by varying the extension and dope concentration of the buried base region, forming a constant or variable dope concentration profile of the buried base region, providing or not a base sinker, and varying the form and distance of the base sinker from the emitter region.

Abstract translation: 集成在具有N型衬底和形成表面的N型外延层的半导体材料晶片中的垂直PNP晶体管。 晶体管具有跨越衬底和外延层的P型掩埋集电极区域; 将外延阱与晶片的其余部分绝缘的收集器沉降片; 增加调制型N型掩埋基极区域，跨越所述掩埋的集电极区域和所述外延槽，并且形成具有所述外延阱的基极区域; 和外延阱中的P型发射极区。 N +型基底沉降片从表面延伸穿过外延槽延伸到掩埋的基底区域。 晶体管的增益可以通过改变掩埋基极区域的延伸和掺杂浓度来调节，形成掩埋基极区域的恒定或可变掺杂浓度分布，提供或不提供基底沉降片，并且改变晶体管的形式和距离 来自发射极区域的基极沉降片。

公开(公告)号：US6104073A

公开(公告)日：2000-08-15

申请号：US903511

申请日：1997-07-30

Applicant: Paolo Ferrari ,  Mario Foroni ,  Benedetto Vigna ,  Flavio Villa

Inventor： Paolo Ferrari ,  Mario Foroni ,  Benedetto Vigna ,  Flavio Villa

IPC: G01P15/02 ,  B81B3/00 ,  B81C1/00 ,  G01P15/08 ,  G01P15/125 ,  H01L29/84 ,  H01L29/82 ,  H01L21/00 ,  H01L27/01 ,  H01L27/20

CPC classification number: G01P15/0802 ,  G01P15/125 ,  G01P2015/0814

Abstract: The acceleration sensor is formed in a monocrystalline silicon wafer forming part of a dedicated SOI substrate presenting a first and second monocrystalline silicon wafer separated by an insulting layer having an air gap. A well is formed in the second wafer over the air gap and is subsequently trenched up to the air gap to release the monocrystalline silicon mass forming the movable mass of the sensor; the movable mass has two numbers of movable electrodes facing respective pluralities of fixed electrodes. In the idle condition, each movable electrode is separated by different distances from the two fixed electrodes facing the movable electrode.

Abstract translation: 加速度传感器形成在形成由具有气隙的绝缘层分离的第一和第二单晶硅晶片的专用SOI衬底的一部分的单晶硅晶片中。 在空气间隙中的第二晶片中形成一个阱，然后将其向上延伸到气隙以释放形成传感器的可移动质量块的单晶硅质量块; 可移动物体具有面对多个固定电极的两个可动电极数。 在空闲状态下，每个可移动电极与面对可动电极的两个固定电极分开不同的距离。

公开(公告)号：US6087729A

公开(公告)日：2000-07-11

申请号：US62378

申请日：1998-04-17

Applicant: Gianfranco Cerofolini ,  Giorgio De Santi ,  Giuseppe Crisenza

Inventor： Gianfranco Cerofolini ,  Giorgio De Santi ,  Giuseppe Crisenza

IPC: C01B33/12 ,  C08F292/00 ,  C08L51/10 ,  H01B3/30 ,  H01L21/312 ,  H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L23/485

CPC classification number: H01B3/30 ,  C08F292/00 ,  H01L23/5329 ,  H01L2924/0002 ,  Y02P20/544

Abstract: An insulating film between stacked electrically conducting layers through which interconnections of integrated circuits are realized, is formed of an aerogel of an inorganic oxide on which organic monomers have been grafted under inert ion bombardment and successively further incorporated in the aerogel to fill at least partially the porosities of the inorganic aerogel. The composite dielectric material is thermally stable and has a satisfactory thermal budget. The method of forming an aerogel film includes the spinning of a precursor compound solution onto the wafer followed by supercritical solvent extraction carried out in the spinning chamber.

Abstract translation: 层叠的导电层之间的绝缘膜通过其形成集成电路的互连，其中无机氧化物的气凝胶由有机单体在惰性离子轰击下接枝并依次进一步掺入气凝胶中以至少部分地填充 无机气凝胶的孔隙率。 复合介电材料是热稳定的并且具有令人满意的热预算。 形成气凝胶膜的方法包括将前体化合物溶液旋转到晶片上，然后在纺丝室中进行超临界溶剂萃取。

公开(公告)号：US06078203A

公开(公告)日：2000-06-20

申请号：US19893

申请日：1998-02-06

Applicant: Alessandro Zafarana ,  Franco Cocetta ,  Mauro Merlo

Inventor： Alessandro Zafarana ,  Franco Cocetta ,  Mauro Merlo

IPC: H02M3/156 ,  H02P9/30 ,  H03K5/04

CPC classification number: H02P9/305 ,  H02M3/156

Abstract: A voltage regulator of the type comprising a linear filter, a comparator, and a stretcher filter which are connected in cascade with one another between an input terminal and an output terminal of the regulator. The input terminal receives an error signal as converted by the comparator into a square-wave error signal, and the output terminal deliveres a square-wave output control signal which has a stretched duty cycle over the square-wave error signal by a time delay introduced from the stretcher filter. The regulator further comprises a non-linear filtering section for the error signal which is connected between the input terminal of the regulator and the linear filter and has linear gain with the error signal below a first value, gain approximately of unity with the error signal between the first value and a second value, and zero gain with the error signal above the second value.

Abstract translation: 一种类型的电压调节器，包括在调节器的输入端子和输出端子之间彼此级联连接的线性滤波器，比较器和担架滤波器。 输入端子将由比较器转换的误差信号接收为方波误差信号，输出端子通过时间延迟引出方波输出控制信号，该方波输出控制信号在方波误差信号上具有拉伸占空比 从担架过滤器。 调节器还包括用于误差信号的非线性滤波部分，其连接在调节器的输入端和线性滤波器之间并具有线性增益，误差信号低于第一值，增益大约为1， 第一个值和第二个值，零增益，误差信号高于第二个值。

公开(公告)号：US6075338A

公开(公告)日：2000-06-13

申请号：US3206

申请日：1998-01-06

Applicant: Ettore Mazza ,  Biagio Russo ,  Biagio Giacalone ,  Jean-Marie Bourgeois

Inventor： Ettore Mazza ,  Biagio Russo ,  Biagio Giacalone ,  Jean-Marie Bourgeois

IPC: H02P27/08 ,  H02P5/34

CPC classification number: H02P27/08 ,  Y10S706/90

Abstract: Driving of a three-phase motor includes controlling the slip of the motor by way of a fuzzy logic algorithm. The simplicity and precision of the fuzzy control of the slip permits dynamically optimizing the efficiency of a three-phase motor under any operating condition, and thereby minimizing power consumption. The control is carried out by knowing: the effective speed of the motor that represents the feedback value, and that may be provided by a common encoder (typically a dynamo or an optic device) keyed on the motor's spindled; the stator frequency imposed on the motor; the required speed; and, of course, the characteristic curve (frequency-torque) of the motor.

Abstract translation: 三相电动机的驱动包括通过模糊逻辑算法来控制电动机的滑移。 滑动模糊控制的简单性和精度允许在任何操作条件下动态优化三相电动机的效率，从而最小化功耗。 控制是通过知道：表示反馈值的电动机的有效速度，并且可以由键合在电动机上的公共编码器（通常是发电机或光学装置）提供; 定子频率施加在电机上; 所需速度; 当然也是马达的特性曲线（频率转矩）。

公开(公告)号：US6072359A

公开(公告)日：2000-06-06

申请号：US108081

申请日：1998-06-30

Applicant: Davide Brambilla ,  Daniela Nebuloni ,  Giorgio Rossi ,  Sergio Lecce

Inventor： Davide Brambilla ,  Daniela Nebuloni ,  Giorgio Rossi ,  Sergio Lecce

IPC: G05F3/26 ,  H03F3/345 ,  H03F3/343

CPC classification number: H03F3/345 ,  G05F3/267

Abstract: A current generator circuit with controllable frequency response has at least one current mirror formed of MOS transistors, being powered through a terminal held at a constant voltage, having an input leg through which a reference current (I1) is driven by a first current generator (G1), and having an output leg for generating, on an output terminal (OUT) of the mirror, a mirrored current (I.sub.out) which is proportional to the reference current (I1). The input leg includes at least a first transistor (M1) which is diode-connected and has a control terminal (Ga1) coupled to a corresponding terminal (Ga2) of a second transistor (M2) included in the output leg. In accordance with the invention, the mirror circuit also has an impedance matching circuit connected across the control terminals (Ga1 and Ga2) of the first and second transistors and configured to hold the same voltage value at both terminals (Ga1 and Ga2). The impedance matching circuit has an adjustable output impedance, specifically lower in value than the value to be had without this circuit. It functions to regulate the impedance on the control node (Ga2) of the second transistor (M2). The invention is equally applicable to N-channel and P-channel MOS transistors. Advantageously, the reference current can be varied by an external signal which is a function of the output signal, to provide feedback regulating features.

Abstract translation: 具有可控频率响应的电流发生器电路具有由MOS晶体管形成的至少一个电流镜，其通过保持在恒定电压的端子供电，具有输入支路，参考电流（I1）由第一电流发生器 G1），并且具有用于在镜的输出端（OUT）上产生与参考电流（I1）成比例的镜像电流（Iout）的输出支路。 输入支路至少包括二极管连接的第一晶体管（M1），并且具有耦合到包括在输出支路中的第二晶体管（M2）的相应端子（Ga2）的控制端子（Ga1）。 根据本发明，镜电路还具有连接在第一和第二晶体管的控制端（Ga1和Ga2）两端的阻抗匹配电路，并被配置为在两端（Ga1和Ga2）处保持相同的电压值。 阻抗匹配电路具有可调节的输出阻抗，具体值低于没有该电路的值。 它用于调节第二晶体管（M2）的控制节点（Ga2）上的阻抗。 本发明同样适用于N沟道和P沟道MOS晶体管。 有利地，参考电流可以通过作为输出信号的函数的外部信号来改变，以提供反馈调节特征。