公开(公告)号：US06876042B1

公开(公告)日：2005-04-05

申请号：US10653105

申请日：2003-09-03

Applicant: Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

Inventor： Bin Yu ,  Shibly S. Ahmed ,  Haihong Wang

IPC: H01L21/336 ,  H01L29/786 ,  H01L29/76 ,  H01L27/01

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A FinFET includes a fin formed on an insulating layer and a first gate material layer formed proximate to sides of the fin. The FinFET further includes a protective layer formed above the first gate material layer and the fin, and a second gate material layer formed above the protective layer and the fin. The second gate material layer may be formed into a gate for the fin that may be biased independently of gate(s) formed from the first gate material layer, thus providing additional design flexibility in controlling the potential in the fin during on/off switching of the FinFET.

Abstract translation: FinFET包括形成在绝缘层上的鳍和靠近鳍的侧面形成的第一栅极材料层。 FinFET还包括形成在第一栅极材料层和鳍上方的保护层，以及形成在保护层和鳍上方的第二栅极材料层。 第二栅极材料层可以形成为可以独立于由第一栅极材料层形成的栅极偏置的鳍的栅极，从而在控制鳍的电位的开/关切换期间提供额外的设计灵活性 FinFET。

公开(公告)号：US06855607B2

公开(公告)日：2005-02-15

申请号：US10459495

申请日：2003-06-12

Applicant: Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Krishnashree Achuthan ,  Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: C09G1/02 ,  H01L21/3105 ,  H01L21/321 ,  H01L21/336 ,  H01L29/423 ,  H01L29/49 ,  H01L29/786

CPC classification number: H01L29/785 ,  C09G1/02 ,  H01L21/31053 ,  H01L21/3212 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/66795 ,  H01L29/6681 ,  Y10S438/959

Abstract: A method of manufacturing a MOSFET type semiconductor device includes planarizing a gate material layer that is deposited over a channel. The planarization is performed in a multi-step process that includes an initial “rough” planarization and then a “fine” planarization. The slurry used for the finer planarization may include added material that tends to adhere to low areas of the gate material.

公开(公告)号：US06787439B2

公开(公告)日：2004-09-07

申请号：US10290276

申请日：2002-11-08

Applicant: Shibly S. Ahmed ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Cyrus E. Tabery ,  Haihong Wang ,  Bin Yu

IPC: H01L213205

CPC classification number: H01L29/42384 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7853

Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator. The fin structure may include side surfaces and a top surface. The method may also include depositing a gate material over the fin structure and planarizing the deposited gate material. An antireflective coating may be deposited on the planarized gate material, and a gate structure may be formed out of the planarized gate material using the antireflective coating.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上形成翅片结构。 翅片结构可以包括侧表面和顶表面。 该方法还可以包括在鳍结构上沉积栅极材料并平坦化沉积的栅极材料。 可以在平坦化的栅极材料上沉积抗反射涂层，并且可以使用抗反射涂层从平坦化栅极材料形成栅极结构。

公开(公告)号：US06787402B1

公开(公告)日：2004-09-07

申请号：US09845604

申请日：2001-04-27

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L21355

CPC classification number: H01L29/785 ,  H01L29/66795

Abstract: A double-gate vertical MOSFET transistor is described along with an associated fabrication method. The MOSFET transistor is configured with separate gates on each side of a vertical source-drain channel that is capped by an insulation layer. The fabrication process generally comprises forming a silicon-insulator stack having a silicon fin (channel) capped with insulation. The opposing ends of the silicon-insulator stack being configured with areas capable of receiving source and drain contacts. The vertical surfaces of the silicon fin are insulated prior to the formation of gate electrodes adjacent the two opposing sides of the silicon-insulator stack. By way of example, the gate electrodes are formed by depositing a thick layer of conductive gate material over the substrate and then removing the adjoining upper portion, such as by polishing. Portions of each gate electrode are configured with areas capable of receiving a gate contact.

Abstract translation: 描述双栅垂直MOSFET晶体管以及相关的制造方法。 MOSFET晶体管在垂直源极 - 漏极沟道的每一侧配置有分隔的栅极，该栅极被绝缘层封住。 制造工艺通常包括形成具有用绝缘体封盖的硅片（通道）的硅 - 绝缘体堆叠。 硅 - 绝缘体堆叠的相对端被配置有能够接收源极和漏极接触的区域。 在形成邻近硅 - 绝缘体堆叠的两个相对侧的栅电极之前，硅片的垂直表面被绝缘。 作为示例，栅电极通过在衬底上沉积厚的导电栅极材料层，然后例如通过抛光去除邻接的上部而形成。 每个栅电极的部分配置有能够接收栅极接触的区域。

公开(公告)号：US06764884B1

公开(公告)日：2004-07-20

申请号：US10405342

申请日：2003-04-03

Applicant: Bin Yu ,  Haihong Wang

Inventor： Bin Yu ,  Haihong Wang

IPC: H01L2184

CPC classification number: H01L29/785 ,  H01L29/42392 ,  H01L29/66545 ,  H01L29/66818

Abstract: A method of manufacturing a FinFET device includes forming a fin structure on an insulating layer. The fin structure includes a conductive fin. The method also includes forming source/drain regions and forming a dummy gate over the fin. The dummy gate may be removed and the width of the fin in the channel region may be reduced. The method further includes depositing a gate material to replace the removed dummy gate.

Abstract translation: 制造FinFET器件的方法包括在绝缘层上形成翅片结构。 翅片结构包括导电翅片。 该方法还包括形成源极/漏极区域并在鳍片上形成虚拟栅极。 可以去除伪栅极，并且可以减小沟道区域中的鳍的宽度。 该方法还包括沉积栅极材料以取代去除的虚拟栅极。

公开(公告)号：US06743689B1

公开(公告)日：2004-06-01

申请号：US10341427

申请日：2003-01-14

Applicant: Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

Inventor： Eric N. Paton ,  Robert B. Ogle ,  Cyrus E. Tabery ,  Qi Xiang ,  Bin Yu

IPC: H01L21336

CPC classification number: H01L21/26513 ,  H01L21/26506 ,  H01L21/2658 ,  H01L21/268 ,  H01L29/458 ,  H01L29/66492 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66553 ,  H01L29/66772 ,  H01L29/78612 ,  H01L29/78621

Abstract: Semiconductor devices comprising fully and partially depleted SOI transistors with accurately defined monocrystalline or substantially completely monocrystalline silicon source/drain extensions are fabricated by selectively pre-amorphizing intended source/drain extensions, ion implanting dopants into the pre-amorphized regions and laser thermal annealing to effect crystallization and activation of the source/drain extensions. Embodiments include forming a gate electrode over an SOI substrate with a gate dielectric layer therebetween, forming silicon nitride sidewall spacers on the side surfaces of the gate electrode, forming source/drain regions, forming a thermal oxide layer on the gate electrode and on the source/drain regions, removing the silicon nitride sidewall spacers, pre-amorphizing the intended source/drain extension regions, ion implanting impurities into the pre-amorphized regions and laser thermal annealing to crystallize the pre-amorphized regions and to activate the source/drain extensions.

Abstract translation: 包括具有精确定义的单晶或基本上完全单晶硅源极/漏极延伸的完全和部分耗尽的SOI晶体管的半导体器件通过将预期的源/漏延伸，离子注入掺杂剂预先非晶化以进行预非晶化区域和激光热退火来制造 源/漏扩展的结晶和激活。 实施例包括在SOI衬底之上形成栅极电介质层，在栅电极之间形成氮化硅侧壁间隔物，形成源/漏区，在栅电极和源极上形成热氧化层 漏极区域，去除氮化硅侧壁间隔物，使预期的源极/漏极延伸区域预非晶化，离子注入杂质到预非晶化区域和激光热退火以使预非晶化区域结晶并激活源极/漏极延伸部分 。

公开(公告)号：US06703277B1

公开(公告)日：2004-03-09

申请号：US10118437

申请日：2002-04-08

Applicant: Eric N. Paton ,  Bin Yu

Inventor： Eric N. Paton ,  Bin Yu

IPC: H01L218242

CPC classification number: H01L21/31691 ,  H01L21/28176 ,  H01L21/28194 ,  H01L21/28291 ,  H01L21/3115 ,  H01L21/31155 ,  H01L28/56 ,  H01L29/513 ,  H01L29/517 ,  H01L29/78

Abstract: A semiconductor device and a process for fabricating the device, the process including steps of depositing on the silicon substrate a layer comprising at least one high-K dielectric material, whereby a quantity of silicon dioxide is formed at an interface between the silicon substrate and the high-K dielectric material layer; depositing on the high-K dielectric material layer a layer of a metal; and diffusing the metal through the high-K dielectric material layer, whereby the metal reduces at least a portion of the silicon dioxide to silicon and the metal is oxidized to form a dielectric material having a K value greater than silicon dioxide. In another embodiment, the metal is implanted into the interfacial layer. A semiconductor device including such metal layer and implanted metal is also provided.

Abstract translation: 一种半导体器件和用于制造该器件的工艺，该工艺包括以下步骤：在硅衬底上沉积包含至少一种高K电介质材料的层，由此在硅衬底与硅衬底之间的界面处形成一定数量的二氧化硅 高K介电材料层; 在高K电介质材料层上沉积一层金属; 并且通过高K电介质材料层使金属扩散，由此金属将至少一部分二氧化硅还原为硅，并且金属被氧化以形成K值大于二氧化硅的电介质材料。 在另一个实施方案中，将金属注入界面层。 还提供了包括这种金属层和植入金属的半导体器件。

公开(公告)号：US06693333B1

公开(公告)日：2004-02-17

申请号：US09846912

申请日：2001-05-01

Applicant: Bin Yu

Inventor： Bin Yu

IPC: H01L2976

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: An integrated circuit can include gate structures designed to effect a work function of a transistor. A first set of gate structures can have a first work function and a second set of gate structures can have a second work function. The gate structures include metal layers to affect changes in the work function. The work function can affect the threshold voltage associated with the transistors. The transistor can be built on a silicon-on-insulator substrate.

Abstract translation: 集成电路可以包括设计用于实现晶体管的功函数的栅极结构。 第一组门结构可以具有第一功函数，第二组门结构可以具有第二功函数。 栅极结构包括影响功函数变化的金属层。 工作功能可以影响与晶体管相关的阈值电压。 晶体管可以建立在绝缘体上硅衬底上。

公开(公告)号：US06686231B1

公开(公告)日：2004-02-03

申请号：US10310777

申请日：2002-12-06

Applicant: Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

Inventor： Shibly S. Ahmed ,  Haihong Wang ,  Bin Yu

IPC: H01L2100

CPC classification number: H01L29/785 ,  H01L29/42384 ,  H01L29/66545 ,  H01L29/66795

Abstract: A method of manufacturing a semiconductor device may include forming a fin structure on an insulator and forming a gate structure over a channel portion of the fin structure. The method may also include forming a sacrificial oxide layer around the gate structure and removing the gate structure to define a gate recess within the sacrificial oxide layer. A metal gate may be formed in the gate recess, and the sacrificial oxide layer may be removed.

Abstract translation: 制造半导体器件的方法可以包括在绝缘体上形成翅片结构，并在翅片结构的沟道部分上形成栅极结构。 该方法还可以包括在栅极结构周围形成牺牲氧化物层并去除栅极结构以在牺牲氧化物层内限定栅极凹槽。 可以在栅极凹部中形成金属栅极，并且可以去除牺牲氧化物层。

公开(公告)号：US06660578B1

公开(公告)日：2003-12-09

申请号：US10118274

申请日：2002-04-08

Applicant: Olov Karlsson ,  Qi Xiang ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic

Inventor： Olov Karlsson ,  Qi Xiang ,  HaiHong Wang ,  Bin Yu ,  Zoran Krivokapic

IPC: H01L218238

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: A semiconductor device, a semiconductor wafer and a method of forming a semiconductor wafer where a barrier layer is used to inhibit P-type ion-penetration into a dielectric layer made from a high-K material.

Abstract translation: 半导体器件，半导体晶片和形成半导体晶片的方法，其中阻挡层用于抑制由高K材料制成的电介质层中的P型离子渗透。