公开(公告)号：US3904969A

公开(公告)日：1975-09-09

申请号：US44918474

申请日：1974-03-07

Applicant: MOTOROLA INC

Inventor： EASTMOND BRUCE C

IPC: H03G3/34 ,  H04B1/12

CPC classification number: H03G3/342

Abstract: Squelch circuit responsive to the periodicity of a voice signal for controlling the output of a radio receiver to provide transmission of speech and reject noise. The audio signal from the receiver is amplitude limited and the transitions in the limited wave control a bistable multivibrator having first and second out-of-phase outputs. The outputs are used to activate circuits which produce voltage samples proportional to the time period between zero crossings, with the alternate periods producing voltages across two capacitors. The difference between the successive voltage samples is derived and compared with a reference voltage to provide a control voltage. The control voltage, which is produced as long as the difference between the samples is less than the reference, is applied to a gate circuit which controls the charging of a squelch control capacitor. A control voltage which continues through a plurality of samples causes the voltage across the squelch control capacitor to raise to a level which operates a squelch switch to allow transmission of the audio signal.

Abstract translation: 响应于语音信号的周期性的静噪电路，用于控制无线电接收机的输出以提供语音和拒绝噪声的传输。 来自接收机的音频信号受到幅度限制，并且受限波中的转换控制具有第一和第二异相输出的双稳态多谐振荡器。 输出用于激活产生与过零点之间的时间段成比例的电压采样的电路，交替周期产生两个电容器两端的电压。 导出连续电压样本之间的差异，并与参考电压进行比较以提供控制电压。 只要样本之间的差小于参考值就产生的控制电压被施加到控制静噪控制电容器的充电的门电路。 继续通过多个采样的控制电压使得静噪控制电容器两端的电压升高到操作静噪开关以允许音频信号传输的电平。

公开(公告)号：US3898684A

公开(公告)日：1975-08-05

申请号：US49443774

申请日：1974-08-05

Applicant: MOTOROLA INC

Inventor： DAVIDSOHN URYON S

IPC: H01L27/088 ,  H01L27/092 ,  H01L29/00 ,  H01L29/06 ,  H01L29/78 ,  H01L27/02

CPC classification number: H01L29/0638 ,  H01L27/088 ,  H01L27/092 ,  H01L29/00

Abstract: Metal-oxide-silicon field effect transistors (MOSFET) are shown utilizing diffusion guarding of the gate electrode of a MOSFET device and utilizing the drain of one MOSFET device as the source of the next integrally formed MOSFET device. Other types of isolation shown include the surrounding of a functional unit with a source diffusion area, and/or permanently connecting a gate electrode to a potential level for preventing signal flow past such a gate.

公开(公告)号：US3898484A

公开(公告)日：1975-08-05

申请号：US40935073

申请日：1973-10-24

Applicant: MOTOROLA INC

Inventor： WILCOX MILTON E

IPC: H03K4/64 ,  H03K5/00

CPC classification number: H03K4/64

Abstract: A horizontal processing circuit in monolithic integrated circuit form for a television receiver, which processing circuit includes a horizontal oscillator, phase comparator, and predriver stage. The oscillator generates a sawtooth signal at approximately the desired frequency as determined by an external RC timing network, and which is locked in phase and frequency to the received television signal by the actions of the phase comparator. The sawtooth signal is applied to the predriver stage which includes an electronic switch which when conductive produces an output pulse of essentially square wave configuration. By controlling the setting of the switching threshold of the electronic switch the width of the output pulse may be effectively controlled within a predetermined range or ratio such that the horizontal processing circuit may be rendered fully compatible within any horizontal sweep system whatever the design factors may be.

Abstract translation: 一种用于电视接收机的单片集成电路形式的水平处理电路，该处理电路包括水平振荡器，相位比较器和预驱动级。 振荡器产生大约由外部RC定时网络确定的期望频率的锯齿波信号，并且通过相位比较器的动作将其与相位和频率锁定到接收的电视信号。 锯齿波信号被施加到预驱动级，其包括电子开关，当导电产生基本上为方波构型的输出脉冲时。 通过控制电子开关的切换阈值的设置，可以有效地控制输出脉冲的宽度在预定范围或比例内，使得水平处理电路可以在任何水平扫描系统内完全兼容，无论设计因素可以是什么 。

公开(公告)号：US3897323A

公开(公告)日：1975-07-29

申请号：US49500574

申请日：1974-08-05

Applicant: MOTOROLA INC

Inventor： SCHLOTTHAUER ROY

IPC: C25D5/02

CPC classification number: C25D5/02

Abstract: A method of selective or ''''spot'''' plating, particularly electroplating, of articles including the steps of masking predetermined portions of the article to be plated so that those portions will not be contacted by the plating solution, establishing an electrical connection to conductive portions of the article and then contacting the unmasked portions of the article with plating solution, for sufficient length of time to plate those portions. The apparatus includes means for feeding the article into an apertured conveyor belt which forms the mask between the portions of the article to be plated and those portions which are not to be plated. The masked portion of the article is then contacted by a conductive liquid and the unmasked portion of the article contacted by the plating solution, through means of a reciprocating plating head which travels with the conveyor for a sufficient length of time to affect the plating of the unmasked portions of the article.

Abstract translation: 一种选择性或“点”电镀，特别是电镀的方法，包括以下步骤：掩蔽待镀制品的预定部分，使得这些部分不会被电镀液接触，建立与电镀液的导电部分的电连接 然后将制品的未掩蔽部分与电镀溶液接触足够长的时间以将这些部分压平。 该装置包括用于将物品送入有孔传送带的装置，该带状传送带在要被镀制品的部分和不被镀覆的部分之间形成掩模。 然后，制品的掩模部分接触导电液体和与镀液接触的制品的未掩蔽部分，通过往复式电镀头，该往复电镀头与输送机一起行走足够长的时间以影响电镀 文章的未屏蔽部分。

公开(公告)号：US3895239A

公开(公告)日：1975-07-15

申请号：US42853173

申请日：1973-12-26

Applicant: MOTOROLA INC

Inventor： ALASPA ALLAN A

IPC: G06F1/24 ,  H03K17/22 ,  H03K17/284 ,  H03K17/20 ,  H03K21/32

CPC classification number: H03K17/223 ,  H03K17/284

Abstract: An automatic power-on reset circuit adapted for use on complementary MOS integrated circuit semiconductor dies is provided. The circuit includes a voltage reference stage followed by an amplifier stage. A PN diode is coupled in series with a diode-connected MOSFET and a low current MOSFET device to provide a slight overdrive to the P-channel MOSFET of a CMOS inverter, which determines the initial output level thereof. As the voltage applied to the power supply conductor increases, the switching point of the amplifier-inverter stage varies until the output thereof assumes the opposite logic level. This transition of the output of the amplifier inverter stage is applied to wave shaping circuitry and an output circuit which reliably produces the desired reset signal.

Abstract translation: 提供一种适用于互补MOS集成电路半导体管芯的自动上电复位电路。 该电路包括一个电压基准级，随后是放大级。 PN二极管与二极管连接的MOSFET和低电流MOSFET器件串联耦合，以向CMOS反相器的P沟道MOSFET提供轻微的过驱动，其确定其初始输出电平。 当施加到电源导体的电压增加时，放大器 - 反相器级的切换点变化，直到其输出呈现相反的逻辑电平。 放大器逆变器级的输出的这种转变被应用于波形整形电路和可靠地产生期望的复位信号的输出电路。

公开(公告)号：US3894290A

公开(公告)日：1975-07-08

申请号：US37051873

申请日：1973-06-15

Applicant: MOTOROLA INC

Inventor： SCHOEFF JOHN A

IPC: H03F3/343 ,  H03F3/34 ,  H03F3/347 ,  H03F3/45 ,  H03F3/04

CPC classification number: H03F3/45071 ,  H03F3/45479

Abstract: A converter circuit for transforming balanced signals into an unbalanced output signal is disclosed. First and second active loads each of which are connected between one of the output terminals of a balanced source, such as a differential amplifier, and a voltage supply are included in the converter circuit. The loads clamp each of the output terminals of the differential amplifier to a predetermined voltage level. A third active load interconnects the balanced loads with each other, provides current regulation for the differential amplifier and facilitates a ''''turn-around'''' function which enables each of the balanced output signals of the differential amplifier to at all times contribute to the unbalanced output signal.

Abstract translation: 公开了一种用于将平衡信号变换为不平衡输出信号的A转换器电路。 在转换器电路中包括第一和第二有源负载，每个有源负载连接在诸如差分放大器的平衡源的输出端之一和电压源之间。 负载将差分放大器的每个输出端子钳位到预定的电压电平。 第三个有源负载将平衡负载彼此互连，为差分放大器提供电流调节，并有助于“转向”功能，使得差分放大器的每个平衡输出信号总是有助于不平衡的输出信号 。

公开(公告)号：US3893149A

公开(公告)日：1975-07-01

申请号：US46108974

申请日：1974-04-15

Applicant: MOTOROLA INC

Inventor： GRENON LAWRENCE A

IPC: H01L27/15 ,  G08B5/36

CPC classification number: H01L27/156 ,  Y10S257/926

Abstract: There is disclosed a monolithic light display comprising a matrix of light emitting diodes in an integral structure which is scannable to produce an alpha numeric character display. Each of the light emitting diodes is electrically isolated from each other diode in a supporting carrier, with the cathodes of the diodes connected in a series of groups by address lines and anodes connected in an orthagonal plurality of groups by bit lines or column lines. A strobing format logic address system is provided for lighting the individual diodes to emission for producing an alpha numeric character. There is also disclosed a method of making the foregoing which comprises moat etching a semiconductor substrate of a first conductivity to form a plurality of mesas in an orthagonal pattern desired for the ultimate alpha numeric display. A region of the opposite conductivity is then produced on the moat etched surface of the substrate by diffusing a suitable dopant therein. The PN junction is thereby formed following the contour of the moat etched surface. A layer of material is then deposited upon the diffused surface and a supporting carrier deposited over the first layer. If the first layer is of conductive material, the supporting carrier is required to be of dielectric material. If the first layer is of a dielectric material, the carrier may be either dielectric, heat conductive, or electrically conductive material. The original substrate is then removed by lapping, etching or polishing to leave only the mesas in a dielectrically isolated array. Suitable electrical connections are made to the individual diodes to complete the display.

公开(公告)号：US3892608A

公开(公告)日：1975-07-01

申请号：US44683474

申请日：1974-02-28

Applicant: MOTOROLA INC

Inventor： KUHN GREGORY L

IPC: H01L21/00 ,  H01L21/3213 ,  H01L21/3215 ,  H01L21/763 ,  H01L7/34 ,  H01L7/36 ,  H01L7/50

CPC classification number: H01L21/763 ,  H01L21/00 ,  H01L21/32134 ,  H01L21/32155 ,  Y10S148/051 ,  Y10S148/085 ,  Y10S148/102 ,  Y10S148/118 ,  Y10S148/122 ,  Y10S438/924

Abstract: A process is disclosed for filling grooves, moats, and channels formed by both channel and anisotropic etching techniques. Basically the process is a two-step process to be performed on a wafer in which a channel and/or a moat has been formed. A P+ (boron) doped oxide is placed in the grooves or moats using spinon techniques followed by a uniform deposition of polycrystalline silicon over the entire wafer. Due to the spinning effects the P+ doped oxide is collected mostly in the grooves or moats. The P+ doped oxide that remains outside of the grooves and/or moats is removed using standard photolithographic procedures. The wafer is now heated to a temperature sufficient to drive the boron impurities from the P+ doped oxide into the polycrystalline silicon. A portion of a polycrystalline silicon now becomes heavily P+ doped. The remaining polycrystalline silicon remains undoped. The wafer is then etched by an etchant which effectively stops when the material being etched is highly P+ doped. In this manner a portion of the remaining undoped polycrystalline material is removed and the highly doped polycrystalline material is left in the channels and/or moats. The above can be repeated until the moats or channels are completely filled.

公开(公告)号：US3889287A

公开(公告)日：1975-06-10

申请号：US42237773

申请日：1973-12-06

Applicant: MOTOROLA INC

Inventor： POWELL MICHAEL W

IPC: H01L27/112 ,  G11C17/00 ,  G11C17/08 ,  H01L21/8246 ,  H01L21/8247 ,  H01L21/86 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792 ,  H01L11/00 ,  H01L15/00

CPC classification number: H01L27/12 ,  H01L21/86 ,  Y10S148/053 ,  Y10S148/122 ,  Y10S148/15 ,  Y10S148/151

Abstract: A semiconductor memory of a matrix of active devices each of which is metal-nitride-oxide-silicon (MNOS) field effect transistor device. Each of the active devices defines one bit of the memory. A polycrystalline silicon member defines the gate electrode for the active device and also the row conductor for the matrix. The source and drain electrodes of columns of the field effect transistors are interconnected in parallel with other source and drain electrodes of single crystal silicon of the field effect devices to define column conductors for the matrix. The matrix is manufactured by providing an insulating substrate having a layer of monocrystalline silicon thereon. The monocrystalline silicon is suitably masked and etched to define a plurality of parallel ladder-like structures wherein the side pieces of the ladder form the column conductors for the matrix while the cross pieces or the rungs of the ladder define the channel of the device. The shaped monocrystalline silicon material and the exposed substrate is then covered by a layer of silicon dioxide, a layer of silicon nitride and a layer of polycrystalline silicon utilizing suitable masking and etching steps. The polycrystalline silicon, the silicon-nitride and silicon-dioxide are removed to form the row conductors and gate electrodes for the active devices, while exposing portions of the side pieces of the ladders of semiconductor material. A single diffusion step is then required to create the source and drain junctions for the active devices; render conductive the column conductors; and render conductive the gate electrode and row conductors formed by the polycrystalline silicon, that portion of the monocrystalline silicon on the substrate underlying the gate electrode being masked by the gate electrode so as to define the channel in the originally deposited rung of the monocrystalline silicon.

Abstract translation: 一种有源器件矩阵的半导体存储器，每个半导体存储器是金属氮化物 - 氧化物 - 硅（MNOS）场效应晶体管器件。 每个活动设备定义存储器的一位。 多晶硅构件限定用于有源器件的栅极电极以及用于基体的行导体。 场效应晶体管的列的源极和漏极电极与场效应器件的单晶硅的其它源极和漏极并联互连，以定义用于矩阵的列导体。

公开(公告)号：US3887373A

公开(公告)日：1975-06-03

申请号：US42413873

申请日：1973-12-12

Applicant: MOTOROLA INC

Inventor： HAYS ROBERT G ,  HUGHES HENRY G ,  HUNTER WILLIAM L

IPC: G03F7/008 ,  G03F7/32 ,  G03F7/08

CPC classification number: G03F7/008 ,  G03F7/325 ,  Y10S430/12

Abstract: Photoresist compositions including 2,6-bis(p-azidobenzylidene)4-methylcyclohexanone and cyclized polyisoprene rubber dissolved in saturated aliphatic or cyclo-aliphatic hydrocarbons or other non-aromatic, saturated solvents having solubility parameter values close to that of polyisoprene.

Abstract translation: 溶解在饱和脂肪族或环脂族烃或其他非芳族饱和溶剂中的2,6-双（对叠氮基亚苄基）-4-甲基环己酮和环化聚异戊二烯橡胶的光致抗蚀剂组合物，其溶解度参数值接近聚异戊二烯的溶度参数值。