公开(公告)号：US07670894B2

公开(公告)日：2010-03-02

申请号：US12150898

申请日：2008-04-30

Applicant: Willy Rachmady ,  Marko Radosavljevic ,  Mantu K. Hudait ,  Matthew V Metz

Inventor： Willy Rachmady ,  Marko Radosavljevic ,  Mantu K. Hudait ,  Matthew V Metz

IPC: H01L21/8238 ,  H01L21/44

CPC classification number: H01L21/0228 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/28273 ,  H01L21/312 ,  H01L21/3141 ,  H01L21/31641 ,  H01L21/31645 ,  H01L29/517 ,  H01L29/78

Abstract: Embodiments of the present invention describe a method of fabricating a III-V quantum well transistor with low current leakage and high on-to-off current ratio. A hydrophobic mask having an opening is formed on a semiconductor film. The opening exposes a portion on the semiconductor film where a dielectric layer is desired to be formed. A hydrophilic surface is formed on the exposed portion of the semiconductor film. A dielectric layer is then formed on the hydrophilic surface by using an atomic layer deposition process. A metal layer is deposited on the dielectric layer.

Abstract translation: 本发明的实施例描述了一种制造具有低电流泄漏和高导通截止电流比的III-V量子阱晶体管的方法。 在半导体膜上形成具有开口的疏水性掩模。 该开口暴露出希望形成介电层的半导体膜上的一部分。 亲水表面形成在半导体膜的暴露部分上。 然后通过使用原子层沉积工艺在亲水表面上形成介电层。 金属层沉积在电介质层上。

公开(公告)号：US20090321717A1

公开(公告)日：2009-12-31

申请号：US12164982

申请日：2008-06-30

Applicant: Ravi Pillarisetty ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Willy Rachmady ,  Titash Rakshit

Inventor： Ravi Pillarisetty ,  Mantu K. Hudait ,  Marko Radosavljevic ,  Gilbert Dewey ,  Willy Rachmady ,  Titash Rakshit

IPC: H01L29/12 ,  H01L21/336

CPC classification number: H01L29/7784 ,  H01L29/201 ,  H01L29/4236 ,  H01L29/66462

Abstract: A compositionally-graded quantum well channel for a semiconductor device is described. A semiconductor device includes a semiconductor hetero-structure disposed above a substrate and having a compositionally-graded quantum-well channel region. A gate electrode is disposed in the semiconductor hetero-structure, above the compositionally-graded quantum-well channel region. A pair of source and drain regions is disposed on either side of the gate electrode.

Abstract translation: 描述了用于半导体器件的组成级分量子阱沟道。 半导体器件包括设置在衬底之上并具有组成级分的量子阱沟道区的半导体异质结构。 在半导体异质结构中，栅极电极设置在成分梯度的量子阱沟道区之上。 一对源区和漏区设置在栅电极的两侧。

公开(公告)号：US20090283496A1

公开(公告)日：2009-11-19

申请号：US11391920

申请日：2006-03-28

Applicant: Marko Radosavljevic ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Suman Datta

Inventor： Marko Radosavljevic ,  Jack T. Kavalieros ,  Amlan Majumdar ,  Suman Datta

IPC: B44C1/22 ,  B05D5/12

CPC classification number: B82Y40/00 ,  B82Y30/00 ,  C01B32/162

Abstract: Embodiments of the invention include apparatuses and methods relating to directed carbon nanotube growth using a patterned layer. In some embodiments, the patterned layer includes an inhibitor material that directs the growth of carbon nanotubes.

Abstract translation: 本发明的实施例包括与使用图案化层的定向碳纳米管生长相关的装置和方法。 在一些实施方案中，图案化层包括引导碳纳米管生长的抑制剂材料。

公开(公告)号：US20090140301A1

公开(公告)日：2009-06-04

申请号：US11947157

申请日：2007-11-29

Applicant: Mantu K. Hudait ,  Marko Radosavljevic ,  Suman Datta

Inventor： Mantu K. Hudait ,  Marko Radosavljevic ,  Suman Datta

IPC: H01L29/94 ,  H01L21/336

CPC classification number: H01L29/20 ,  H01L21/28575 ,  H01L29/452 ,  H01L29/456

Abstract: Reducing contact resistance in p-type field effect transistors is generally described. In one example, an apparatus includes a first semiconductor substrate, a first noble metal film including palladium (Pd) coupled with the first semiconductor substrate, a second noble metal film including platinum (Pt) coupled with the first noble metal film, and a third metal film including an electrically conductive metal coupled with the second noble metal film, wherein the first, second, and third metal films form one or more contacts having reduced specific contact resistance between the first semiconductor substrate and the one or more contacts.

Abstract translation: 通常描述在p型场效应晶体管中降低接触电阻。 在一个实例中，一种装置包括第一半导体衬底，包括与第一半导体衬底耦合的钯（Pd）的第一贵金属膜，包含与第一贵金属膜耦合的铂（Pt）的第二贵金属膜，以及第三贵金属膜 金属膜包括与第二贵金属膜耦合的导电金属，其中第一，第二和第三金属膜形成一个或多个具有降低的第一半导体衬底和一个或多个触点之间的比接触电阻的触点。

公开(公告)号：US07279375B2

公开(公告)日：2007-10-09

申请号：US11173866

申请日：2005-06-30

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark L. Doczy ,  Justin K. Brask ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Brian S. Doyle ,  Jack Kavalieros ,  Mark L. Doczy ,  Justin K. Brask ,  Uday Shah ,  Suman Datta ,  Robert S. Chau

IPC: H01L21/336

CPC classification number: H01L29/785 ,  H01L29/41791 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/78681 ,  H01L29/78684 ,  H01L2029/7858

Abstract: A contact architecture for nanoscale channel devices having contact structures coupling to and extending between source or drain regions of a device having a plurality of parallel semiconductor bodies. The contact structures being able to contact parallel semiconductor bodies having sub-lithographic pitch.

公开(公告)号：US20070152266A1

公开(公告)日：2007-07-05

申请号：US11322795

申请日：2005-12-29

Applicant: Brian Doyle ,  Justin Brask ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Marko Radosavljevic ,  Robert Chau

Inventor： Brian Doyle ,  Justin Brask ,  Amlan Majumdar ,  Suman Datta ,  Jack Kavalieros ,  Marko Radosavljevic ,  Robert Chau

IPC: H01L29/76

CPC classification number: H01L29/785 ,  H01L29/66545 ,  H01L29/66628 ,  H01L29/66795 ,  H01L29/7848

Abstract: The fabrication of a tri-gate transistor formed with a replacement gate process is described. A nitride dummy gate, in one embodiment, is used allowing the growth of epitaxial source and drain regions immediately adjacent to the dummy gate. This reduces the external resistance.

Abstract translation: 描述了用替换栅极工艺形成的三栅极晶体管的制造。 在一个实施例中，使用氮化物虚拟栅极，允许生长与伪栅极紧邻的外延源极和漏极区域。 这减少了外部电阻。

公开(公告)号：US20070114593A1

公开(公告)日：2007-05-24

申请号：US11285763

申请日：2005-11-21

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Justin Brask ,  Brian Doyle ,  Robert Chau

IPC: H01L29/788 ,  H01L21/336

CPC classification number: G11C13/025 ,  B82Y10/00 ,  G11C2213/17 ,  H01L29/78696 ,  H01L51/0048 ,  H01L51/0541

Abstract: A transistor is described having a source electrode and a drain electrode. The transistor has at least one semiconducting carbon nanotube that is electrically coupled between the source and drain electrodes. The transistor has a gate electrode and dielectric material containing one or more quantum dots between the carbon nanotube and the gate electrode.

Abstract translation: 描述了具有源电极和漏电极的晶体管。 晶体管具有至少一个电耦合在源极和漏极之间的半导体碳纳米管。 晶体管具有在碳纳米管和栅电极之间含有一个或多个量子点的栅电极和电介质材料。

公开(公告)号：US20200211842A1

公开(公告)日：2020-07-02

申请号：US16232535

申请日：2018-12-26

Applicant: Glenn GLASS ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Paul FISCHER ,  Anand MURTHY ,  Walid HAFEZ

Inventor： Glenn GLASS ,  Sansaptak DASGUPTA ,  Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Paul FISCHER ,  Anand MURTHY ,  Walid HAFEZ

IPC: H01L21/02 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L27/092 ,  H01L23/00 ,  H01L29/66 ,  H01L21/306 ,  H01L21/8252

Abstract: An integrated circuit structure comprises a relaxed buffer stack that includes a channel region, wherein the relaxed buffer stack and the channel region include a group III-N semiconductor material, wherein the relaxed buffer stack comprises a plurality of AlGaN material layers and a buffer stack over the plurality of AlGaN material layers, wherein the buffer stack comprises the group III-N semiconductor material and has a thickness of less than approximately 25 nm. A back barrier is in the relaxed buffer stack between the plurality of AlGaN material layers and the buffer stack, wherein the back barrier comprises an AlGaN material of approximately 2-10% Al. A polarization stack over the relaxed buffer stack.

公开(公告)号：US20200098885A1

公开(公告)日：2020-03-26

申请号：US16139248

申请日：2018-09-24

Applicant: Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DUSGUPTA ,  Paul FISCHER ,  Walid HAFEZ

Inventor： Han Wui THEN ,  Marko RADOSAVLJEVIC ,  Sansaptak DUSGUPTA ,  Paul FISCHER ,  Walid HAFEZ

IPC: H01L29/51 ,  H01L29/423 ,  H01L29/778 ,  H01L29/78 ,  H01L29/66 ,  H01L21/28 ,  H01L21/02

Abstract: A transistor comprises a base layer that includes a channel region, wherein the base layer and the channel region include group III-V semiconductor material. A gate stack is above the channel region, the gate stack comprises a gate electrode and a composite gate dielectric stack, wherein the composite gate dielectric stack comprises a first large bandgap oxide layer, a low bandgap oxide layer, and a second large bandgap oxide layer to provide a programmable voltage threshold. Source and drain regions are adjacent to the channel region.

公开(公告)号：US20160308014A1

公开(公告)日：2016-10-20

申请号：US15197563

申请日：2016-06-29

Applicant: Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

Inventor： Marko Radosavljevic ,  Amlan Majumdar ,  Suman Datta ,  Jack T. Kavalieros ,  Brian S. Doyle ,  Justin K. Brask ,  Robert S. Chau

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/06 ,  H01L29/786

CPC classification number: H01L29/42392 ,  H01L21/28079 ,  H01L21/28194 ,  H01L29/0673 ,  H01L29/41775 ,  H01L29/495 ,  H01L29/51 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66606 ,  H01L29/66636 ,  H01L29/66742 ,  H01L29/7834 ,  H01L29/78618 ,  H01L29/78696 ,  Y10S438/926 ,  Y10S438/957

Abstract: A method for fabricating a field-effect transistor with a gate completely wrapping around a channel region is described. Ion implantation is used to make the oxide beneath the channel region of the transistor more etchable, thereby allowing the oxide to be removed below the channel region. Atomic layer deposition is used to form a gate dielectric and a metal gate entirely around the channel region once the oxide is removed below the channel region.

Abstract translation: 描述了一种制造具有完全围绕通道区域的栅极的场效应晶体管的方法。 离子注入用于使晶体管的沟道区下方的氧化物更易蚀刻，从而允许氧化物在沟道区下方被去除。 一旦氧化物在通道区域下方被去除，原子层沉积被用于在通道区域的整个周围形成栅极电介质和金属栅极。