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公开(公告)号：US20180310390A1
公开(公告)日：2018-10-25
申请号：US15957578
申请日：2018-04-19
Applicant: STMicroelectronics (Alps) SAS , STMicroelectronics S.r.l. , STMicroelectronics Application GmbH
Inventor： Philippe SIRITO-OLIVIER , Giovanni Luca TORRISI , Manuel GAERTNER , Fritz BURKHARDT
CPC classification number: H05B39/02 , B60Q1/00 , B60Q3/80 , H05B33/0806 , H05B33/0815 , H05B39/047
Abstract: The power supply device comprises a supply transistor commanded by a command signal and providing electric power to a lighting module, and a driving means configured to selectively generate, depending on an instruction signal representative of the structure of said at least one lighting module, a first command signal able to command the supply transistor into an ohmic regime, a second command signal able to command the supply transistor into a pulse width modulation regime involving an alternation of ohmic regimes and blocked regimes, and a third command signal able to command the supply transistor into a saturated regime.
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公开(公告)号：US10103079B2
公开(公告)日：2018-10-16
申请号：US15659078
申请日：2017-07-25
Inventor： Yvon Imbs , Laurent Schwarz , David Auchere , Laurent Marechal
IPC: H01L23/48 , H01L23/31 , H01L21/56 , H01L21/768 , H01L21/3105 , H01L23/498 , H01L23/66 , H01L23/00
Abstract: An electronic device includes a supporting substrate having a front mounting face and an electrical connection network. An integrated circuit chip is mounted to the mounting face and is electrically connected to the electrical connection network. A primary encapsulation block embeds the integrated circuit chip and extends above and around the integrated circuit chip on the mounting face of the supporting substrate. An opening is provided in the primary encapsulation block to at least partially uncover an electrical contact. An additional wire made from an electrically conductive material has an end that is electrically connected to the electrical contact. An additional encapsulation block above the primary encapsulation block embeds the additional wire.
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公开(公告)号：US20180191318A1
公开(公告)日：2018-07-05
申请号：US15393485
申请日：2016-12-29
Inventor： Vratislav Michal , Michel Ayraud
CPC classification number: H03F3/45179 , G01R1/30 , G01R31/362 , G01R31/3682 , H03F1/0205 , H03F3/45183 , H03F2200/129 , H03F2200/261 , H03F2200/471 , H03F2203/45151
Abstract: A circuit includes an amplifier having a first power terminal configured to be coupled to a supply voltage and a second power terminal configured to be coupled to a reference potential. The circuit further includes a first impedance element coupled between a first input terminal of the amplifier and a first output terminal of the amplifier. The circuit additionally includes a second impedance element coupled between the first input terminal and the reference potential. The amplifier is configured to output a first voltage at a second output terminal of the amplifier in response to the supply voltage being greater than an output voltage at the first output terminal of the amplifier. The amplifier is further configured to output a second voltage at the second output terminal of the amplifier in response to the supply voltage being less than the output voltage at the first output terminal of the amplifier.
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公开(公告)号：US10014834B1
公开(公告)日：2018-07-03
申请号：US15393550
申请日：2016-12-29
Applicant: STMicroelectronics (Alps) SAS
Inventor： Vratislav Michal , Denis Cottin , Patrik Arno , Nicolas Marty
Abstract: An embodiment circuit includes a first voltage divider coupled between a first voltage level and a ground potential. The circuit further includes an error amplifier having a first input terminal coupled to a node between a first resistive element and a second resistive element of the first voltage divider. The circuit further includes a second voltage divider coupled between a second voltage level and a reference voltage, wherein a second input terminal of the error amplifier is coupled to a node between a third resistive element and a fourth resistive element of the second voltage divider, and wherein an output voltage of the error amplifier is configured to control a potential difference between the first voltage level and the second voltage level.
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公开(公告)号：US20180175586A1
公开(公告)日：2018-06-21
申请号：US15598113
申请日：2017-05-17
Applicant: STMicroelectronics (Alps) SAS
Inventor： Xavier Branca
CPC classification number: H01S5/06216 , G01S7/4815 , G01S7/4911 , G01S17/32 , G01S17/89 , H01S5/0428 , H01S5/062 , H01S5/183 , H01S5/4025 , H01S5/405 , H01S5/42 , H01S5/423
Abstract: An optical emitting circuit includes an array of M optical sources distributed in N groups, where N is lower than M. A controller is configured to generate N periodic square wave control signals that are successively mutually phase shifted by pi/N and that all have the same period, and to cyclically activate/deactivate all the optical sources of the N groups using the control signals. The optical emitting circuit is configured so that each group is activated when a corresponding control signal is in its first state and deactivated when the corresponding control signal is in its second state. The number of optical sources in each group and the order of the groups in the sequence of activations/deactivations are chosen so as to generate an optical signal having an amplitude that sinusoidally varies in steps.
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Patent Agency Ranking
公开(公告)号：US09905262B2
公开(公告)日：2018-02-27
申请号：US14918614
申请日：2015-10-21
Inventor： Jonathan Cottinet , Jean Claude Bini
CPC classification number: G11B20/10222 , G06F3/165 , H04B15/04 , H04B2215/065 , H04L7/04
Abstract: A method for transmitting and/or receiving a potential aggressor audio signal includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.
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公开(公告)号：US09754851B2
公开(公告)日：2017-09-05
申请号：US15050253
申请日：2016-02-22
Inventor： David Auchere , Laurent Marechal , Yvon Imbs , Laurent Schwarz
IPC: H01L23/48 , H01L23/31 , H01L21/56 , H01L23/66 , H01Q1/22 , H01L21/3105 , H01L21/48 , H01L23/498
CPC classification number: H01Q1/2283 , H01L21/3105 , H01L21/4853 , H01L21/56 , H01L23/3121 , H01L23/3135 , H01L23/315 , H01L23/49838 , H01L23/66 , H01L2223/6677 , H01L2224/16227 , H01L2924/15311 , H01L2924/1815
Abstract: An electronic device includes a support plate having a mounting face and an electrical connection network. An integrated circuit chip is mounted on the mounting face and linked to the electrical connection network. An en encapsulation block embeds the integrated circuit chip. An additional element made of an electrically conductive material is at least partly embedded within the encapsulation block. The additional conductive element has a main portion extending parallel to the support plate and has a secondary portion that is linked electrically to the integrated circuit chip. An opening is formed in the encapsulation block, and the secondary portion extends into that opening to make the electrical link. The additional conductive element may be an antenna.
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公开(公告)号：US20160232938A1
公开(公告)日：2016-08-11
申请号：US14918614
申请日：2015-10-21
Inventor： Jonathan Cottinet , Jean Claude Bini
CPC classification number: G11B20/10222 , G06F3/165 , H04B15/04 , H04B2215/065 , H04L7/04
Abstract: A method for transmitting and/or receiving a potential aggressor audio signal includes a transmission and/or a reception of successive groups of data timed by a first clock signal within respective successive frames synchronized by a second clock signal. In the presence of a risk of interference of the potential aggressor audio signal with a different, potential victim, signal, during the transmission or reception of the potential aggressor audio signal, the frequency of the first clock signal is modified while keeping the frequency of the second clock signal unchanged.
Abstract translation: 用于发送和/或接收潜在攻击者音频信号的方法包括在由第二时钟信号同步的各个连续帧内由第一时钟信号定时的连续的数据组的发送和/或接收。 在潜在的侵扰者音频信号与潜在的受害者信号的干扰的风险的存在下，在传输或接收潜在的侵扰者音频信号期间，修改第一时钟信号的频率，同时保持第 第二个时钟信号不变。
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公开(公告)号：US12155406B2
公开(公告)日：2024-11-26
申请号：US17881749
申请日：2022-08-05
Inventor： Danika Perrin , Sandrine Nicolas
Abstract: In an embodiment an envelope detection device includes an input terminal configured to receive an amplitude-modulated radio frequency signal, a first resistive element and a first MOS transistor connected in parallel between the input terminal and a first node configured to receive a reference potential, a first capacitive element connected between a gate of the first MOS transistor and the first node, an envelope detection circuit connected to the input terminal and configured to supply a voltage representative of an envelope of the amplitude-modulated signal and a circuit for controlling the first MOS transistor configured to supply a first current to the gate of the first MOS transistor only when the voltage is smaller than a first threshold and draw a second current from the gate of the first MOS transistor only when the voltage is higher than a second threshold, the second threshold being higher than the first threshold.
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公开(公告)号：US12051681B2
公开(公告)日：2024-07-30
申请号：US17374868
申请日：2021-07-13
Inventor： Deborah Cogoni , David Auchere , Laurent Schwartz , Claire Laporte
CPC classification number: H01L25/165 , H01G4/385
Abstract: A device for regulating a voltage of an electric current supplying an integrated circuit resting on a substrate. The integrated circuit comprises a ground terminal and a power supply terminal able to receive the electric current. The regulation device comprises a first cover covering the integrated circuit, a second cover covering the integrated circuit. The first cover is electrically connected to the power supply terminal of the integrated circuit. The second cover is electrically connected to the ground terminal of the integrated circuit. The first cover and the second cover are connected together by a capacitive connection.
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