公开(公告)号：US20130138975A1

公开(公告)日：2013-05-30

申请号：US13751628

申请日：2013-01-28

Applicant: STMicroelectronics S.A.

Inventor： Albert Martinez ,  William Orlando

IPC: G06F21/62 ,  G06F21/60

CPC classification number: G06F21/62 ,  G06F12/1408 ,  G06F12/1483 ,  G06F21/52 ,  G06F21/602 ,  G06F21/79 ,  G06F2212/1052 ,  G06F2221/033 ,  G06F2221/2105

Abstract: A method for loading a program, contained in at least a first memory, into a second memory accessible by an execution unit, in which the program is in a cyphered form in the first memory, a circuit for controlling the access to the second memory is configured from program initialization data, instructions of the program, and at least initialization data being decyphered to be transferred into the second memory after configuration of the circuit.

Abstract translation: 一种用于将包含在至少第一存储器中的程序加载到执行单元可访问的第二存储器中的方法，其中程序处于第一存储器中的加密形式，用于控制对第二存储器的访问的电路是 由程序初始化数据，程序的指令，以及至少初始化数据被解密以在电路配置之后被传送到第二存储器中。

公开(公告)号：US20040268396A1

公开(公告)日：2004-12-30

申请号：US10814818

申请日：2004-03-31

Applicant: STMicroelectronics S.A.

Inventor： Pierre Busson ,  Pierre-Oliver Jouffre ,  Bernard Louis-Gavet

IPC: H04N007/20

CPC classification number: H04N7/20 ,  H04L27/148

Abstract: An integrated circuit is embodied on a monolithic substrate and incorporates a tuning module of the direct sampling type that is able to receive satellite digital television analog signals composed of several channels, as well as several channel decoding digital modules connected at the output of the tuning module so as to deliver respectively simultaneously several streams of data packets corresponding to several different selected channels.

Abstract translation: 集成电路体现在单片基板上，并且包括能够接收由几个通道组成的卫星数字电视模拟信号的直接采样类型的调谐模块，以及连接在调谐模块的输出端的多个通道解码数字模块 以便分别同时传送与若干不同选择的信道相对应的若干数据分组流。

公开(公告)号：US20040263656A1

公开(公告)日：2004-12-30

申请号：US10827094

申请日：2004-04-19

Applicant: STMicroelectronics S.A.

Inventor： Laurent Simony

IPC: H04N005/335

CPC classification number: H04N5/378 ,  H04N5/3575

Abstract: The sampling of a pixel signal by a sampling capacitor is effectuated by applying to the sampling capacitor a voltage equal to the corresponding pixel voltage minus the value of the gate-source voltage of a follower transistor biased with a predetermined constant bias current for a first predetermined duration so as to obtain for the sampling capacitor a final state of stable charge. The bias current is then interrupted. Lastly, the end of the sampling pulse occurs on completion of a second predetermined duration after the said interruption of the current.

Abstract translation: 通过对采样电容器施加等于相应像素电压的电压减去以预定的恒定偏置电流偏置的跟随器晶体管的栅极 - 源极电压的值来实现采样电容器的采样电容的第一预定 持续时间，以便为采样电容器获得稳定电荷的最终状态。 然后中断偏置电流。 最后，采样脉冲的结束在所述电流中断之后的第二预定持续时间完成。

公开(公告)号：US20040230736A1

公开(公告)日：2004-11-18

申请号：US10760631

申请日：2004-01-20

Applicant: STMicroelectronics S.A.

Inventor： Bruno Leconte ,  Sebastien Zink ,  Paola Cavaleri

IPC: G11C005/00

CPC classification number: G11C16/08 ,  G11C8/08

Abstract: An address decoder selectively applies to word lines of a memory array individual signals of variable polarity, negative or positive, the value of which varies according to a word line address applied to the decoder. The decoder comprises a group decoder delivering signals for selecting a group of word lines of variable polarity, at least one subgroup decoder delivering signals for selecting a subgroup of word lines of variable polarity, and word line drivers each comprising means for multiplexing the group and subgroup selection signals, for selecting and selectively applying one of these signals to a word line. Advantages: reduction in the size of the terminating elements of the decoders in relation with the reduction of the technological pitch in Flash memories.

Abstract translation: 地址解码器有选择地应用于存储器阵列的字线，根据应用于解码器的字线地址而变化的可变极性，负或正的各个信号。 解码器包括传送用于选择可变极性字线组的信号的组解码器，传送用于选择可变极性字线子组的信号的至少一个子组解码器，以及字线驱动器，每个字线驱动器包括用于复用组和子组 选择信号，用于选择并选择性地将这些信号中的一个施加到字线。 优点：减少解码器的端接元件的尺寸与减少闪存中技术间距有关。

公开(公告)号：US20040221141A1

公开(公告)日：2004-11-04

申请号：US10779855

申请日：2004-02-17

Applicant: STMicroelectronics S.A.

Inventor： Gosagan Padmanabhan ,  Dragos Davidescu ,  Franck Roche

IPC: G06F009/30

CPC classification number: G06F9/30123 ,  G06F9/3004 ,  G06F9/4486 ,  G06F9/461

Abstract: The present invention relates to a method for managing the stack of a microprocessor comprising a central processing unit and a memory array, the central processing unit comprising registers containing contextual data and a stack pointer, the stack being a zone of the memory array used for saving contextual data upon a switch from a first to a second program. According to the present invention, the method comprises saving contextual data contained in a variable number of registers that varies according to the value of at least one flag stored in a register to be saved. Advantages: optimization of the filling of the stack and of the number of subprograms that can be interleaved.

Abstract translation: 本发明涉及一种用于管理包括中央处理单元和存储器阵列的微处理器的堆叠的方法，所述中央处理单元包括包含上下文数据的寄存器和堆栈指针，所述堆栈是用于保存的存储器阵列的区域 从第一程序切换到第二程序时的上下文数据。 根据本发明，该方法包括保存包含在根据存储在要保存的寄存器中的至少一个标志的值而变化的可变数目的寄存器中的上下文数据。 优点：优化堆栈的填充以及可以交错的子程序数量。

公开(公告)号：US20040210730A1

公开(公告)日：2004-10-21

申请号：US10700361

申请日：2003-11-03

Applicant: STMicroelectronics S.A.

Inventor： Pierre Marty ,  Rey Gaelle ,  Pascal Chauvet

IPC: G06F012/00

CPC classification number: G11C7/22 ,  G06F13/1673

Abstract: A circuit for controlling a memory including at least two areas to which access cannot be had simultaneously, the circuit including first circuitry for storing a series of read and/or write instructions separately for each of the areas, and second circuitry for detecting that a first instruction intended for a first area is a predetermined instruction to be followed by a period during which the first area can receive no other instruction, and third circuitry for, during the period, providing instructions to another memory area.

Abstract translation: 一种用于控制存储器的电路，所述存储器包括不能同时访问的至少两个区域，所述电路包括用于为每个区域分别存储一系列读取和/或写入指令的第一电路，以及用于检测第一 用于第一区域的指令是第一区域不能接收其他指令的周期之后的预定指令，以及在该周期期间向另一个存储区域提供指令的第三电路。

公开(公告)号：US20040143805A1

公开(公告)日：2004-07-22

申请号：US10699613

申请日：2003-10-30

Applicant: STMICROELECTRONICS S.A.

Inventor： Arnaud Deleule

IPC: G06F009/45 ,  H01L029/06

CPC classification number: G03F1/38 ,  H01L23/544 ,  H01L2223/5444 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device for determining the version of metal mask utilized for producing a given metal layer (Metal3) in an integrated circuit including a plurality of metal layers (Meta0, . . . , Metal3), and any modification made to the given metal layer (Metal3) requiring generation of a new version of the corresponding metal mask. The device includes a cell (Cell) integrated into the metal layer (Metal3) including at least a first voltage source (Vdd) for supplying a first voltage level, at least a second voltage source (GND) for supplying a second voltage level, and an output bus composed of at least one conductor wire (S1, S2) connected selectively to one of the first and second voltage sources as a function of the version of metal mask used to produce the metal layer, so as to generate a binary output signal representative of the mask version utilized.

Abstract translation: 一种用于确定用于在包括多个金属层（Meta0，...，Metal3）的集成电路中制造给定金属层（Metal3）的金属掩膜版本的装置，以及对给定金属层（Metal3 ）需要产生相应金属掩模的新版本。 该装置包括集成到金属层（Metal3）中的单元（Cell），其包括用于提供第一电压电平的至少第一电压源（Vdd），用于提供第二电压电平的至少第二电压源（GND）;以及 一个输出总线，其由至少一个导体线（S1，S2）组成，该导体线选择性地连接到第一和第二电压源中的一个，作为用于产生金属层的金属掩模的形式的函数，以便产生二进制输出信号 代表使用的掩模版本。

公开(公告)号：US20040136238A1

公开(公告)日：2004-07-15

申请号：US10697957

申请日：2003-10-30

Applicant: STMicroelectronics S.A.

Inventor： Sylvie Wuidart ,  Luc Wuidart

IPC: G11C011/34

CPC classification number: G11C17/18 ,  G11C11/5692 ,  G11C17/14

Abstract: A memory cell with at least two detectable states among which is an unprogrammed state, comprising, in series between two terminals of application of a read voltage, at least one first branch comprising: a pre-read stage comprising, in parallel, two switchable resistors having different values with a first predetermined difference; and a programming stage formed of a polysilicon programming resistor, a terminal of the programming resistor being accessible by a programming circuit capable of causing an irreversible decrease in its value.

Abstract translation: 具有至少两个可检测状态的存储单元是未编程状态，包括串行施加读取电压的两个端子之间的至少一个第一分支，包括：预读阶段，并联包括两个可切换电阻器 具有第一预定差值的不同值; 以及由多晶硅编程电阻器形成的编程阶段，编程电阻的端子可由能够导致其值不可逆地减小的编程电路访问。

公开(公告)号：US20040119452A1

公开(公告)日：2004-06-24

申请号：US10728582

申请日：2003-12-04

Applicant: STMicroelectronics S.A.

Inventor： Arnaud Florence ,  Jerome Heurtier ,  Franck Galtie

IPC: G05F001/40

CPC classification number: H03K7/08

Abstract: A generator of at least one pulse width modulated signal, including: a generator of a sawtooth signal a generator of high and low reference signals defining, based on a set-point signal, a linear range of each ramp of the sawtooth signal at least one element of comparison of the sawtooth signal with each of the reference signals and at least one element of logic combination of the comparison results, providing the pulse width modulated signal.

Abstract translation: 一种至少一个脉冲宽度调制信号的发生器，包括：锯齿波信号的发生器，高和低参考信号的发生器，其基于设定点信号定义锯齿波信号的每个斜坡的线性范围，至少一个 锯齿波信号与每个参考信号的比较元件以及比较结果的逻辑组合的至少一个元件，提供脉宽调制信号。

公开(公告)号：US20040108571A1

公开(公告)日：2004-06-10

申请号：US10716249

申请日：2003-11-18

Applicant: STMicroelectronics S.A.

Inventor： Olivier Menut ,  Yvon Gris

IPC: H01L029/00

CPC classification number: H01L27/14603 ,  H01L27/1443 ,  H01L27/14643 ,  H01L31/03529 ,  Y02E10/50

Abstract: An integrated circuit is provided that includes a substrate incorporating a semiconductor photodiode device having a p-n junction. The photodiode device includes at least one capacitive trench buried in the substrate and connected in parallel with the junction. In a preferred embodiment, the substrate is formed from silicon, and the capacitive trench includes an internal doped silicon region partially enveloped by an insulating wall that laterally separates the internal region from the substrate. Also provided is a method for fabricating an integrated circuit including a substrate that incorporates a semiconductor photodiode device having a p-n junction.

Abstract translation: 提供一种集成电路，其包括结合有具有p-n结的半导体光电二极管器件的衬底。 该光电二极管装置包括至少一个电容沟槽，该电容沟槽埋设在该衬底中，并与该结点并联连接。 在优选实施例中，衬底由硅形成，并且电容沟槽包括由绝缘壁部分包围的内部掺杂硅区域，该绝缘壁横向分离内部区域与衬底。 还提供了一种制造集成电路的方法，该集成电路包括具有p-n结的半导体光电二极管器件的衬底。