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    Semiconductor Constructions and Memory Arrays
    174.
    发明申请
    Semiconductor Constructions and Memory Arrays 有权
    半导体构造和存储器阵列

    公开(公告)号：US20140319447A1

    公开(公告)日：2014-10-30

    申请号：US14323922

    申请日：2014-07-03

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Cinzia Perrone

    IPC: H01L45/00 ,  H01L27/24 ,  H01L23/48

    CPC classification number: H01L45/141 ,  H01L23/481 ,  H01L23/5256 ,  H01L27/2463 ,  H01L27/2472 ,  H01L27/2481 ,  H01L45/06 ,  H01L45/122 ,  H01L45/1253 ,  H01L45/126 ,  H01L45/144 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: Some embodiments include semiconductor constructions having an electrically conductive interconnect with an upper surface, and having an electrically conductive structure over the interconnect. The structure includes a horizontal first portion along the upper surface and a non-horizontal second portion joined to the first portion at a corner. The second portion has an upper edge. The upper edge is offset relative to the upper surface of the interconnect so that the upper edge is not directly over said upper surface. Some embodiments include memory arrays.

    Abstract translation: 一些实施例包括具有与上表面的导电互连并且在互连上具有导电结构的半导体结构。 该结构包括沿着上表面的水平的第一部分和在拐角处连接到第一部分的非水平的第二部分。 第二部分具有上边缘。 上边缘相对于互连的上表面偏移，使得上边缘不直接在所述上表面上方。 一些实施例包括存储器阵列。

    Memory constructions comprising thin films of phase change material
    175.
    发明授权
    Memory constructions comprising thin films of phase change material 有权
    包含相变材料薄膜的记忆结构

    公开(公告)号：US08729522B2

    公开(公告)日：2014-05-20

    申请号：US13658691

    申请日：2012-10-23

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli

    IPC: H01L29/02

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144

    Abstract: Some embodiments include memory constructions having a film of phase change material between first and second materials; with the entirety of film having a thickness of less than or equal to about 10 nanometers. The memory constructions are configured to transit from one memory state having a first phase of the phase change material to a second memory state having a second phase of the phase change material, and are configured so that an entirety of the phase change material film changes from the first phase to the second phase in transitioning from the first memory state to the second memory state. In some embodiments, at least one of the first and second materials may be carbon, W, TiN, TaN or TiAlN. In some embodiments, at least one of the first and second materials may be part of a structure having bands of two or more different compositions.

    Abstract translation: 一些实施例包括在第一和第二材料之间具有相变材料膜的记忆结构; 整个膜的厚度小于或等于约10纳米。 存储器结构被配置为从具有相变材料的第一相的一个存储器状态转移到具有相变材料的第二相的第二存储器状态，并且被配置为使得整个相变材料膜从 从第一存储器状态转换到第二存储器状态的第一阶段到第二阶段。 在一些实施例中，第一和第二材料中的至少一种可以是碳，钨，钛，钽或钛。 在一些实施方案中，第一和第二材料中的至少一种可以是具有两种或更多种不同组成的带的结构的一部分。

    Memory constructions
    176.
    发明授权
    Memory constructions 有权
    内存结构

    公开(公告)号：US08729519B2

    公开(公告)日：2014-05-20

    申请号：US13658676

    申请日：2012-10-23

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Agostino Pirovano

    IPC: H01L29/02

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/00 ,  H01L45/12 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/144

    Abstract: Some embodiments include memory constructions having a plurality of bands between top and bottom electrically conductive materials. The bands include chalcogenide bands alternating with non-chalcogenide bands. In some embodiments, there may be least two of the chalcogenide bands and at least one of the non-chalcogenide bands. In some embodiments, the memory cells may be between a pair of electrodes; with one of the electrodes being configured as a lance, angled plate, container or beam. In some embodiments, the memory cells may be electrically coupled with select devices, such as, for example, diodes, field effect transistors or bipolar junction transistors.

    Abstract translation: 一些实施例包括在顶部和底部导电材料之间具有多个带的记忆结构。 这些带包括与非硫属化物带交替的硫属化物带。 在一些实施方案中，可以存在至少两个硫族化物带和至少一个非硫族化物带。 在一些实施例中，存储器单元可以在一对电极之间; 其中一个电极被配置为喷枪，倾斜板，容器或梁。 在一些实施例中，存储器单元可以与诸如二极管，场效应晶体管或双极结型晶体管的选择器件电耦合。

    MEMORY CONSTRUCTIONS COMPRISING THIN FILMS OF PHASE CHANGE MATERIAL
    177.
    发明申请
    MEMORY CONSTRUCTIONS COMPRISING THIN FILMS OF PHASE CHANGE MATERIAL 有权
    包含相变材料薄膜的记忆体构造

    公开(公告)号：US20140110658A1

    公开(公告)日：2014-04-24

    申请号：US13658691

    申请日：2012-10-23

    Applicant: MICRON TECHNOLOGY, INC.

    Inventor： Andrea Redaelli

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L27/2445 ,  H01L45/1233 ,  H01L45/1293 ,  H01L45/144

    Abstract: Some embodiments include memory constructions having a film of phase change material between first and second materials; with the entirety of film having a thickness of less than or equal to about 10 nanometers. The memory constructions are configured to transit from one memory state having a first phase of the phase change material to a second memory state having a second phase of the phase change material, and are configured so that an entirety of the phase change material film changes from the first phase to the second phase in transitioning from the first memory state to the second memory state. In some embodiments, at least one of the first and second materials may be carbon, W, TiN, TaN or TiAlN. In some embodiments, at least one of the first and second materials may be part of a structure having bands of two or more different compositions.

    Abstract translation: 一些实施例包括在第一和第二材料之间具有相变材料膜的记忆结构; 整个膜的厚度小于或等于约10纳米。 存储器结构被配置为从具有相变材料的第一相的一个存储器状态转移到具有相变材料的第二相的第二存储器状态，并且被配置为使得整个相变材料膜从 从第一存储器状态转换到第二存储器状态的第一阶段到第二阶段。 在一些实施例中，第一和第二材料中的至少一种可以是碳，钨，钛，钽或钛。 在一些实施方案中，第一和第二材料中的至少一种可以是具有两种或更多种不同组成的带的结构的一部分。

    FORMING RESISTIVE RANDOM ACCESS MEMORIES TOGETHER WITH FUSE ARRAYS
    178.
    发明申请
    FORMING RESISTIVE RANDOM ACCESS MEMORIES TOGETHER WITH FUSE ARRAYS 有权
    形成电阻随机访问记忆与保险丝阵列

    公开(公告)号：US20140048763A1

    公开(公告)日：2014-02-20

    申请号：US14066308

    申请日：2013-10-29

    Applicant: Micron Technology, Inc.

    Inventor： Andrea Redaelli ,  Agostino Pirovano ,  Umberto M. Meotto ,  Giorgio Servalli

    IPC: H01L45/00

    CPC classification number: H01L45/06 ,  H01L23/5256 ,  H01L27/2445 ,  H01L27/2463 ,  H01L45/12 ,  H01L45/1226 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/16 ,  H01L45/1675 ,  H01L45/1683

    Abstract: A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.

    Abstract translation: 可以在具有熔丝阵列的同一基板上形成电阻随机存取存储器阵列。 随机存取存储器和熔丝阵列可以使用相同的活性材料。 例如，熔丝阵列和存储器阵列都可以使用硫族化物材料作为有源开关材料。 主阵列可以使用垂直组沟槽隔离的图案，并且熔丝阵列可以仅使用一组平行沟槽隔离。 结果，熔丝阵列可以具有在相邻沟槽隔离之间连续延伸的导电线。 在一些实施例中，该连续线可以减小通过保险丝的导电路径的电阻。

    Techniques for forming self-aligned memory structures
    179.
    发明授权
    Techniques for forming self-aligned memory structures 有权

    公开(公告)号：US12219883B2

    公开(公告)日：2025-02-04

    申请号：US17881274

    申请日：2022-08-04

    Applicant: Micron Technology, Inc.

    Inventor： Stephen W. Russell ,  Andrea Redaelli ,  Innocenzo Tortorelli ,  Agostino Pirovano ,  Fabio Pellizzer ,  Lorenzo Fratin

    IPC: H10N70/00 ,  H10B63/00 ,  H10N70/20

    Abstract: Methods, systems, and devices for techniques for forming self-aligned memory structures are described. Aspects include etching a layered assembly of materials including a first conductive material and a first sacrificial material to form a first set of channels along a first direction that creates a first set of sections. An insulative material may be deposited within each of the first set of channels and a second sacrificial material may be deposited onto the first set of sections and the insulating material. A second set of channels may be etched into the layered assembly of materials along a second direction that creates a second set of sections, where the second set of channels extend through the first and second sacrificial materials. Insulating material may be deposited in the second set of channels and the sacrificial materials removed leaving a cavity. A memory material may be deposited in the cavity.

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