公开(公告)号：US09064890B1

公开(公告)日：2015-06-23

申请号：US14223545

申请日：2014-03-24

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L21/8238

CPC classification number: H01L29/66545 ,  H01L21/823431 ,  H01L21/823807 ,  H01L21/823821 ,  H01L29/66795 ,  H01L29/785

Abstract: One method disclosed includes, among other things, forming an initial fin, covering a top surface and a portion of the sidewalls of the initial fin structure with etch stop material, forming a sacrificial gate structure above and around the initial fin structure, forming a sidewall spacer adjacent the sacrificial gate structure, performing at least one process operation to remove the sacrificial gate structure and thereby define a replacement gate cavity, performing at least one etching process through the replacement gate cavity to remove a portion of the initial fin structure so as to thereby define a final fin structure and a channel cavity positioned below the final fin structure, and substantially filling the channel cavity with an insulating material.

Abstract translation: 公开的一种方法包括形成初始翅片，用蚀刻停止材料覆盖初始翅片结构的顶表面和一部分侧壁，在初始翅片结构的上方和周围形成牺牲栅结构，形成侧壁 邻近牺牲栅极结构的间隔件，执行至少一个处理操作以去除牺牲栅极结构，从而限定替换栅极腔，通过替代栅极腔执行至少一个蚀刻工艺以去除初始鳍结构的一部分，从而 从而限定最终翅片结构和位于最终翅片结构下方的通道腔，并且用绝缘材料基本上填充通道腔。

公开(公告)号：US09029920B2

公开(公告)日：2015-05-12

申请号：US13909328

申请日：2013-06-04

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Vimal Kamineni ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L21/283 ,  H01L21/8234 ,  H01L29/66

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/283 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures with reduced gate and/or contact resistances and fabrication methods are provided. The method includes: providing a semiconductor device, which includes forming a transistor of the semiconductor device, where the transistor forming includes: forming a T-shaped gate for the transistor, the T-shaped gate being T-shaped in elevational cross-section; and forming an inverted-T-shaped contact to an active region of the transistor, the inverted-T-shaped contact including a conductive structure with an inverted T-shape in elevational cross-section.

Abstract translation: 提供具有减小的栅极和/或接触电阻的半导体结构和制造方法。 该方法包括：提供半导体器件，其包括形成半导体器件的晶体管，其中晶体管形成包括：形成用于晶体管的T形栅极，T形栅极呈垂直截面为T形; 并且在晶体管的有源区域形成倒T形的接触，所述倒T形接触件包括在横截面上具有倒T形的导电结构。

公开(公告)号：US20140327088A1

公开(公告)日：2014-11-06

申请号：US14333135

申请日：2014-07-16

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/785

Abstract: One method disclosed herein includes forming a conformal liner layer in a plurality of trenches that define a fin, forming a layer of insulating material above the liner layer, exposing portions of the liner layer, removing portions of the liner layer so as to result in a generally U-shaped liner positioned at a bottom of each of the trenches, performing at least one third etching process on the layer of insulating material, wherein at least a portion of the layer of insulating material is positioned within a cavity of the U-shaped liner layer, and forming a gate structure around the fin. A FinFET device disclosed herein includes a plurality of trenches that define a fin, a local isolation that includes a generally U-shaped liner that defines, in part, a cavity and a layer of insulating material positioned within the cavity, and a gate structure positioned around the fin.

Abstract translation: 本文公开的一种方法包括在限定翅片的多个沟槽中形成共形衬垫层，在衬垫层上方形成绝缘材料层，暴露衬里层的部分，去除衬里层的部分，从而导致 大体呈U形的衬垫，位于每个沟槽的底部，对绝缘材料层进行至少一个第三蚀刻工艺，其中绝缘材料层的至少一部分位于U形的空腔内 衬垫层，并且在翅片周围形成栅极结构。 本文公开的FinFET器件包括限定翅片的多个沟槽，局部隔离，其包括大致U形的衬垫，其部分地限定腔体中定位的空腔和绝缘材料层，以及定位的门结构 围绕翅膀

公开(公告)号：US20140315371A1

公开(公告)日：2014-10-23

申请号：US13864420

申请日：2013-04-17

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L21/762

CPC classification number: H01L21/823821 ,  H01L21/76229 ,  H01L21/76232

Abstract: One method disclosed herein includes forming a plurality of fin-formation trenches in a semiconductor substrate that define a plurality of spaced-apart fins, forming a patterned liner layer that covers a portion of the substrate positioned between the fins while exposing portions of the substrate positioned laterally outside of the patterned liner layer, and performing at least one etching process on the exposed portions of the substrate through the patterned liner layer to define an isolation trench in the substrate, wherein the isolation trench has a depth that is greater than a depth of the fin-formation trenches.

Abstract translation: 本文公开的一种方法包括在半导体衬底中形成限定多个间隔开的翅片的多个翅片形成沟槽，形成图案化的衬里层，该衬底层覆盖位于翅片之间的衬底的一部分，同时使位于衬底 在图案化的衬里层的横向外侧，并且通过图案化的衬里层对衬底的暴露部分执行至少一个蚀刻工艺，以在衬底中限定隔离沟槽，其中隔离沟槽的深度大于 鳍形沟渠。

公开(公告)号：US08846477B2

公开(公告)日：2014-09-30

申请号：US13628914

申请日：2012-09-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie

IPC: H01L21/336 ,  H01L21/20 ,  H01L21/36 ,  H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L31/062 ,  H01L31/113 ,  H01L23/34

CPC classification number: H01L29/0649 ,  H01L21/7624 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a sacrificial gate structure above a fin, wherein the sacrificial gate structure is comprised of a sacrificial gate insulation layer, a layer of insulating material, a sacrificial gate electrode layer and a gate cap layer, forming a sidewall spacer adjacent opposite sides of the sacrificial gate structure, removing the sacrificial gate structure to thereby define a gate cavity that exposes a portion of the fin, and forming a replacement gate structure in the gate cavity. One illustrative device disclosed herein includes a plurality of fin structures that are separated by a trench formed in a substrate, a local isolation material positioned within the trench, a gate structure positioned around portions of the fin structures and above the local isolation material and an etch stop layer positioned between the gate structure and the local isolation material within the trench.

Abstract translation: 本文公开的一种说明性方法包括在鳍片上形成牺牲栅极结构，其中牺牲栅极结构包括牺牲栅极绝缘层，绝缘材料层，牺牲栅电极层和栅极盖层，形成侧壁间隔物 牺牲栅极结构的相邻相对侧，去除牺牲栅极结构，从而限定露出翅片的一部分的栅极腔，并在栅极腔中形成替换栅极结构。 本文公开的一个示例性器件包括由形成在衬底中的沟槽分开的多个翅片结构，位于沟槽内的局部隔离材料，围绕鳍结构的部分并位于局部隔离材料之上的栅结构，以及蚀刻 停止层位于沟槽内的栅极结构和局部隔离材料之间。

公开(公告)号：US20140264486A1

公开(公告)日：2014-09-18

申请号：US13839626

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Daniel Pham ,  Xiuyu Cai ,  Balasubramanian Pranatharthiharan ,  Pranita Kulkarni

IPC: H01L29/423 ,  H01L29/78 ,  H01L21/28

CPC classification number: H01L29/4232 ,  H01L21/28247 ,  H01L29/66545 ,  H01L29/78

Abstract: One method includes forming a recessed gate/spacer structure that partially defines a spacer/gate cap recess, forming a gate cap layer in the spacer/gate cap recess, forming a gate cap protection layer on an upper surface of the gate cap layer, and removing portions of the gate cap protection layer, leaving a portion of the gate cap protection layer positioned on the upper surface of the gate cap layer. A device disclosed herein includes a gate/spacer structure positioned in a layer of insulating material, a gate cap layer positioned on the gate/spacer structure, wherein sidewalls of the gate cap layer contact the layer of insulating material, and a gate cap protection layer positioned on an upper surface of the gate cap layer, wherein the sidewalls of the gate cap protection layer also contact the layer of insulating material.

Abstract translation: 一种方法包括形成凹入的栅极/间隔结构，其部分地限定间隔物/栅极盖凹部，在间隔物/栅极盖凹部中形成栅极盖层，在栅极盖层的上表面上形成栅极盖保护层，以及 去除栅极帽保护层的部分，留下栅极盖保护层的一部分位于栅极盖层的上表面上。 本文公开的装置包括定位在绝缘材料层中的栅极/间隔结构，位于栅极/间隔物结构上的栅极盖层，其中栅极盖层的侧壁接触绝缘材料层，栅极盖保护层 定位在栅极盖层的上表面上，其中栅极盖保护层的侧壁也接触绝缘材料层。

公开(公告)号：US20140203376A1

公开(公告)日：2014-07-24

申请号：US13745547

申请日：2013-01-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Xiuyu Cai

IPC: H01L21/762 ,  H01L29/78

CPC classification number: H01L21/76224 ,  H01L21/823431 ,  H01L27/0886 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/7851

Abstract: Methods for fabricating FinFET integrated circuits with uniform fin height and ICs fabricated from such methods are provided. A method includes etching a substrate using an etch mask to form fins. A first oxide is formed between the fins. A first etch stop is deposited on the first oxide. A second oxide is formed on the first etch stop. A second etch stop is deposited on the second oxide. A third oxide is deposited overlying the second etch stop. An STI extends from at least a surface of the substrate to at least a surface of the second etch stop overlying the fins to form a first active region and a second active region. The first etch stop overlying the fins is removed. The third oxide is removed to expose the second etch stop. A gate stack is formed overlying a portion of each of the fins.

Abstract translation: 提供了制造具有均匀翅片高度的FinFET集成电路的方法和由这些方法制造的IC。 一种方法包括使用蚀刻掩模蚀刻衬底以形成鳍片。 在翅片之间形成第一氧化物。 第一蚀刻停止层沉积在第一氧化物上。 在第一蚀刻停止件上形成第二氧化物。 第二蚀刻停止层沉积在第二氧化物上。 沉积在第二蚀刻停止层上的第三氧化物。 STI从衬底的至少一个表面延伸到覆盖鳍片的第二蚀刻停止件的至少一个表面，以形成第一有源区域和第二有源区域。 去除覆盖翅片的第一个蚀刻停止。 去除第三氧化物以暴露第二蚀刻停止。 形成了覆盖每个散热片的一部分的栅极叠层。

公开(公告)号：US20140191324A1

公开(公告)日：2014-07-10

申请号：US13736294

申请日：2013-01-08

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L27/0207 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin.

Abstract translation: 一种方法包括通过图案化的掩模层执行蚀刻工艺，以在限定第一和第二鳍片的衬底中形成沟槽，将邻近第一鳍片的衬垫材料形成第一厚度，将与第二鳍片相邻的衬垫材料形成为不同于第二厚度的第二厚度 所述第一厚度在所述沟槽中形成绝缘材料，所述沟槽邻近所述衬垫材料并且在所述掩模层上方，执行处理操作以去除所述绝缘材料层的部分并暴露所述衬垫材料的部分，执行另一蚀刻工艺以去除部分 所述衬垫材料和所述掩模层将所述第一翅片暴露于第一高度，并且所述第二鳍片具有不同于所述第一高度的第二高度，执行另一蚀刻工艺以限定绝缘材料的厚度减薄层，以及形成栅极结构 围绕第一和第二鳍的一部分。

公开(公告)号：US20140191296A1

公开(公告)日：2014-07-10

申请号：US13735315

申请日：2013-01-07

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述一组装置特征的顶部直接形成第一介电层，并且在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一介电层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

公开(公告)号：US10388754B2

公开(公告)日：2019-08-20

申请号：US15343776

申请日：2016-11-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Kangguo Cheng ,  Ali Khakifirooz ,  Ruilong Xie ,  Tenko Yamashita

IPC: H01L21/20 ,  H01L29/66 ,  H01L29/06 ,  H01L29/78 ,  H01L29/10 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/8234 ,  H01L27/088

Abstract: Semiconductor devices and methods for making the same includes conformally forming a first spacer on multiple fins. A second spacer is conformally formed on the first spacer, the second spacer being formed from a different material from the first spacer. The fins are etched below a bottom level of the first spacer to form a fin cavity. Material from the first spacer is removed to expand the fin cavity. Fin material is grown directly on the etched fins to fill the fin cavity.