公开(公告)号：US20190007786A1

公开(公告)日：2019-01-03

申请号：US15638194

申请日：2017-06-29

Applicant: Texas Instruments Incorporated

Inventor： Swaminathan Sankaran ,  Benjamin Stassen Cook ,  Nathan Brooks ,  Bradley Allen Kramer ,  Mark W. Morgan ,  Baher Haroun

IPC: H04W4/00 ,  H04B5/00 ,  H04L29/06 ,  H04L29/08 ,  G06F13/14

CPC classification number: H04W4/80 ,  G06F13/14 ,  H04B5/0031 ,  H04B5/0075 ,  H04L29/06068 ,  H04L67/12

Abstract: A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver coupled to a near field communication (NFC) coupler located on the substrate. Each module has a housing that surrounds and encloses the substrate. The housing has a port region on a surface of the housing. Each module has a field confiner located between the NFC coupler and the port region on the housing configured to guide electromagnetic energy emanated from the NFC coupler through the port region to a port region of an adjacent module. The port region is offset laterally from the NFC coupler. The field confiner is skewed to provide a pathway between the NFC coupler and the port region.

公开(公告)号：US10171578B1

公开(公告)日：2019-01-01

申请号：US15638146

申请日：2017-06-29

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Nathan Brooks ,  Swaminathan Sankaran ,  Bradley Allen Kramer ,  Mark W. Morgan ,  Baher Haroun

IPC: H04B5/00 ,  H04L29/08 ,  H04B5/02

Abstract: A system is provided in which a set of modules each have a substrate on which is mounted a radio frequency (RF) transmitter and/or an RF receiver. Each module has a housing that surrounds and encloses the substrate. The housing has a port region on a surface of the housing. Each module has a tapered near field communication (NFC) field confiner located between the substrate and the port region on the housing configured to guide electromagnetic energy produced by the RF transmitter to the port region so that it can be emanated to a port region of an adjacent module.

公开(公告)号：US10147672B2

公开(公告)日：2018-12-04

申请号：US15133857

申请日：2016-04-20

Applicant: Texas Instruments Incorporated

Inventor： Yong Lin ,  Sadia Arefin Khan ,  Benjamin Stassen Cook

IPC: H01L23/495 ,  H01L23/31 ,  H01L21/48 ,  H01L21/56

Abstract: An integrated circuit (IC) includes a lead frame that has a set of leads coupled to a corresponding set of pins. A semiconductor die with contacts is coupled to the set of leads. Encapsulating material encloses the semiconductor die, such that the set of pins extend beyond the encapsulating material. An additive coating covers one or more of the plurality of pins.

公开(公告)号：US20180323254A1

公开(公告)日：2018-11-08

申请号：US16023377

申请日：2018-06-29

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Roberto Giampiero Massolini ,  Daniel Carothers

IPC: H01L49/02 ,  H01L21/3065 ,  H01L23/498 ,  H01L21/768 ,  H01L23/495

Abstract: An integrated circuit (IC) includes a circuit substrate having a front side surface and an opposite back side surface. Active circuitry is located on the front side surface. An inductive structure is located within a deep trench formed in the circuit substrate below the backside surface. The inductive structure is coupled to the active circuitry.

公开(公告)号：US20180151470A1

公开(公告)日：2018-05-31

申请号：US15361394

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Archana Venugopal ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/522 ,  H01L23/373 ,  H01L23/00 ,  H01L21/768 ,  H01L21/48

Abstract: An integrated circuit has a substrate and an interconnect region disposed on the substrate. The interconnect region has a plurality of interconnect levels. The integrated circuit includes a thermal routing structure in the interconnect region. The thermal routing structure extends over a portion, but not all, of the integrated circuit in the interconnect region. The thermal routing structure includes a cohered nanoparticle film in which adjacent nanoparticles cohere to each other. The thermal routing structure has a thermal conductivity higher than dielectric material touching the thermal routing structure. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US20180151467A1

公开(公告)日：2018-05-31

申请号：US15361403

申请日：2016-11-26

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/367 ,  H01L23/31 ,  H01L23/522 ,  H01L23/528 ,  H01L23/373 ,  H01L23/00 ,  H01L21/56 ,  H01L21/48 ,  H01L21/02

CPC classification number: H01L21/02354 ,  H01L21/02288 ,  H01L21/56 ,  H01L23/3121 ,  H01L23/34 ,  H01L23/3677 ,  H01L23/373 ,  H01L23/3737 ,  H01L23/4334 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/131 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2924/10253 ,  H01L2924/1033 ,  H01L2924/14 ,  H01L2924/15313 ,  H01L2924/014 ,  H01L2924/00014 ,  H01L2224/32245 ,  H01L2924/00012 ,  H01L2924/00

Abstract: A packaged electronic device includes an integrated circuit and an electrically non-conductive encapsulation material in contact with the integrated circuit. A thermal conduit extends from an exterior of the package, through the encapsulation material, to the integrated circuit. The thermal conduit has a thermal conductivity higher than the encapsulation material contacting the thermal conduit. The thermal conduit includes a cohered nanoparticle film. The cohered nanoparticle film is formed by a method which includes an additive process.

公开(公告)号：US09985335B2

公开(公告)日：2018-05-29

申请号：US14982932

申请日：2015-12-29

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Swaminathan Sankaran

IPC: H01Q1/22 ,  H01Q13/20 ,  H04B10/90

CPC classification number: H01Q1/2283 ,  H01Q13/20 ,  H04B10/90

Abstract: In an example arrangement an apparatus includes a semiconductor substrate having a front side surface including circuitry and a backside surface opposing the front side surface; a plurality of metal conductors formed over a front side surface of the semiconductor substrate; at least one cavity opening etched in a backside surface of the semiconductor substrate; and a radiator formed in a portion of the metal conductors and configured to radiate signals through the cavity opening in the backside surface. Methods and additional apparatus arrangements are also disclosed.

公开(公告)号：US20170324446A1

公开(公告)日：2017-11-09

申请号：US15146965

申请日：2016-05-05

Applicant: Texas Instruments Incorporated

Inventor： Benjamin Stassen Cook ,  Swaminathan Sankaran

IPC: H04B5/00 ,  H01Q7/00 ,  H01P3/16

Abstract: A system is provided in which a first waveguide has a first resonator coupled to an end of the first waveguide. A second waveguide has a second resonator coupled to the second waveguide. The first resonator is spaced apart from the second resonator by a gap distance. Transmission of a signal propagated by the first waveguide across the gap to the second waveguide is enhanced by a confined near field mode magnetic field produced by the first resonator in response to the propagating wave that is coupled to the second resonator.

公开(公告)号：US20170309553A1

公开(公告)日：2017-10-26

申请号：US15133857

申请日：2016-04-20

Applicant: Texas Instruments Incorporated

Inventor： Yong Lin ,  Sadia Arefin Khan ,  Benjamin Stassen Cook

IPC: H01L23/495 ,  H01L21/56 ,  H01L21/48 ,  H01L23/31

CPC classification number: H01L23/49558 ,  H01L21/4842 ,  H01L21/565 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/49541 ,  H01L2224/48247 ,  H01L2224/97 ,  H01L2924/181 ,  H01L2924/00012

Abstract: An integrated circuit (IC) includes a lead frame that has a set of leads coupled to a corresponding set of pins. A semiconductor die with contacts is coupled to the set of leads. Encapsulating material encloses the semiconductor die, such that the set of pins extend beyond the encapsulating material. An additive coating covers one or more of the plurality of pins.

公开(公告)号：US09793214B1

公开(公告)日：2017-10-17

申请号：US15438174

申请日：2017-02-21

Applicant: Texas Instruments Incorporated

Inventor： Archana Venugopal ,  Benjamin Stassen Cook ,  Luigi Colombo ,  Robert Reid Doering

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/532 ,  H01L23/522 ,  H01L23/66

CPC classification number: H01L23/53276 ,  H01L23/5226 ,  H01L23/53214 ,  H01L23/53271 ,  H01L23/66 ,  H01L2223/6616

Abstract: An integrated circuit includes an interconnect which includes a metal layer, a layer of graphene on at least one of the top surface of the interconnect or the bottom surface of the interconnect, and a layer of hexagonal boron nitride (hBN) on the layer of graphene, opposite from the metal layer. Dielectric material of the integrated circuit contacts the layer of hBN. The layer of graphene has one or more atomic layers of graphene. The layer of hBN is one to three atomic layers thick. The interconnect may have a lower graphene layer on the bottom surface of the metal layer with a lower hBN layer, and an upper graphene layer on the top surface of the metal layer, with an upper hBN layer.