公开(公告)号：US5470771A

公开(公告)日：1995-11-28

申请号：US658773

申请日：1991-02-21

Applicant: Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

Inventor： Tetsuo Fujii ,  Minekazu Sakai ,  Akira Kuroyanagi

IPC: H01L21/28 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L21/3215

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11524 ,  H01L29/7883

Abstract: A gate oxide film is formed on a surface of a semiconductor substrate. A tunnel insulating film having a thickness smaller than that of the gate insulating film is formed in a portion thereof corresponding to a tunnel region. A first silicon film having a low impurity concentration is formed on the gate insulating film. A second silicon film having an impurity concentration higher than that of the first silicon film is formed on the first silicon film so as to be connected thereto. A third silicon film is formed on the second silicon film through an insulating film. The second and third silicon films are formed into floating and control gates, respectively, thereby forming a semiconductor memory device.

Abstract translation: 在半导体衬底的表面上形成栅极氧化膜。 在对应于隧道区域的部分中形成厚度小于栅极绝缘膜厚度的隧道绝缘膜。 在栅极绝缘膜上形成杂质浓度低的第一硅膜。 在第一硅膜上形成杂质浓度高于第一硅膜的第二硅膜，以便与第一硅膜连接。 通过绝缘膜在第二硅膜上形成第三硅膜。 第二和第三硅膜分别形成浮动和控制栅极，从而形成半导体存储器件。

公开(公告)号：US5403769A

公开(公告)日：1995-04-04

申请号：US213450

申请日：1994-03-15

Applicant: Tetsuo Fujii

Inventor： Tetsuo Fujii

IPC: H01L23/552 ,  H01L27/088 ,  H01L27/12 ,  H01L21/76

CPC classification number: H01L27/12 ,  H01L23/552 ,  H01L27/088 ,  H01L2924/0002 ,  Y10S148/012 ,  Y10S148/05 ,  Y10S148/135

Abstract: A process for producing a semiconductor device of the type having a semiconductor substrate; a semiconductor layer disposed on the semiconductor substrate; a first element formed in a region of the semiconductor layer and having a perimeter including a bottom; a second element formed in another region of the semiconductor layer; an insulating layer surrounding the perimeter of the first element, for electrically insulating and separating the first element from the second element and the semiconductor substrate; an electrical shield layer disposed between the insulating layer and the first element, surrounding the perimeter of the first element, and adapted to a reference electric potential applied thereto, for shielding the first element from an electrical fluctuation of the semiconductor substrate caused by the second element; and an electrode for applying the reference electric potential to the electrical shield layer.

Abstract translation: 一种具有半导体衬底的半导体器件的制造方法; 设置在所述半导体衬底上的半导体层; 形成在所述半导体层的区域中并且具有包括底部的周边的第一元件; 形成在所述半导体层的另一区域中的第二元件; 围绕所述第一元件的周边的绝缘层，用于将所述第一元件与所述第二元件和所述半导体基板电绝缘和分离; 电屏蔽层，设置在所述绝缘层和所述第一元件之间，围绕所述第一元件的周边，并且适于施加到其上的参考电位，用于屏蔽所述第一元件免受所述第二元件引起的所述半导体衬底的电波动 ; 以及用于将参考电位施加到电气屏蔽层的电极。

公开(公告)号：US5306942A

公开(公告)日：1994-04-26

申请号：US829591

申请日：1992-02-03

Applicant: Tetsuo Fujii

Inventor： Tetsuo Fujii

IPC: H01L23/552 ,  H01L27/088 ,  H01L27/12 ,  H01L27/02 ,  H01L25/04 ,  H01L27/04

CPC classification number: H01L27/12 ,  H01L23/552 ,  H01L27/088 ,  H01L2924/0002 ,  Y10S148/012 ,  Y10S148/05 ,  Y10S148/135

Abstract: A semiconductor layer is disposed on a semiconductor substrate and a first element is formed in a region of the semiconductor layer. A second element is formed in another region of the semiconductor layer. An insulating layer surrounds the perimeter of the first element, for electrically insulating and separating the first element from the second element and the semiconductor substrate. An electrical shield layer surrounds the perimeter of the first element, and is adapted to a reference electric potential applied thereto, for shielding the first element from an electrical fluctuation of the semiconductor substrate caused by the second element. An electrode is provided for applying the reference electric potential to the electrical shield layer.

Abstract translation: 半导体层设置在半导体衬底上，第一元件形成在半导体层的区域中。 第二元件形成在半导体层的另一区域中。 绝缘层围绕第一元件的周边，用于将第一元件与第二元件和半导体衬底电绝缘和分离。 电屏蔽层围绕第一元件的周边，并且适用于施加到其上的参考电位，用于屏蔽第一元件与由第二元件引起的半导体衬底的电波动。 提供电极以将参考电位施加到电屏蔽层。

公开(公告)号：US4975390A

公开(公告)日：1990-12-04

申请号：US132573

申请日：1987-12-08

Applicant: Tetsuo Fujii ,  Susumu Kuroyanagi ,  Akira Kuroyanagi ,  Tomohiro Funahashi ,  Minekazu Sakai ,  Shinji Yoshihara

Inventor： Tetsuo Fujii ,  Susumu Kuroyanagi ,  Akira Kuroyanagi ,  Tomohiro Funahashi ,  Minekazu Sakai ,  Shinji Yoshihara

IPC: G01L9/00

CPC classification number: G01L9/0042 ,  G01L9/0055 ,  Y10S148/012 ,  Y10S148/135

Abstract: Herein disclosed is a semiconductor pressure sensor and a method of manufacture. The sensor includes a plate having a recess in its main surface. A diaphragm has a lower surface therof bonded to a first main surface of the plate and formed so as to have an upper surface having no holes therein. A piezoresistive layer is formed so as to be in contact with the diaphragm and is positioned so as to be at least partially over the recess. The resistance of the piezoresistive layer provides an indication of pressure applied to the diaphragm. The manufacturing method includes forming a piezoresistive layer of a single crystal substrate in a diaphragm without any recrystallization.

Abstract translation: 这里公开的是半导体压力传感器和制造方法。 传感器包括在其主表面上具有凹部的板。 隔膜具有与板的第一主表面接合的下表面，并且形成为具有在其中没有孔的上表面。 压阻层形成为与隔膜接触并定位成至少部分地位于凹部上方。 压阻层的电阻提供了施加到隔膜的压力的指示。 制造方法包括在隔膜中形成单晶基板的压阻层，而不会再结晶。

公开(公告)号：US4963505A

公开(公告)日：1990-10-16

申请号：US260997

申请日：1988-10-21

Applicant: Tetsuo Fujii ,  Susumu Kuroyanagi ,  Yukio Tsuzuki

Inventor： Tetsuo Fujii ,  Susumu Kuroyanagi ,  Yukio Tsuzuki

IPC: H01L21/762 ,  H01L21/763 ,  H01L27/088

CPC classification number: H01L21/76248 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/763 ,  H01L21/76272 ,  H01L21/76275 ,  H01L21/76286 ,  H01L27/088 ,  Y10S148/012 ,  Y10S438/969

Abstract: Disclosed is a semiconductor device which comprises a substrate, an insulating film formed at a predetermined region in the substrate or on the main surface of the substrate, a polycrystalline semiconductor layer formed on at least the insulating film, a single crystal semiconductor layer formed on at least the polycrystalline semiconductor layer, an isolation region formed to extend from the top main surface of the single crystal semiconductor layer to at least the surface of the insulating film, through the polycrystalline semiconductor layer, to electrically isolate a portion formed in the single crystal semiconductor layer surrounded by the isolation region from another portion formed in the single crystal semiconductor layer and not surrounded by the isolation region, at least a semiconductor device formed within the portion surrounded by the isolation region. This semiconductor device has an additional characteristics in that another semiconductor device using another main surface of the substrate as the electrode is provided on the surface of the substrate and the single cyrstal semiconductor layer, and the polycrystalline semiconductor layer serves to terminate the electric line of force emitted from the substrate, and therefore, the single crystal semiconductor layer mounted on the polycrystalline semiconductor layer is not affected by the electric line of force. Consequently, a semiconductor device which can operate effectively without being influenced by variations of the electric potential in the substrate can be obtained, and further, an intelligent type power device can be formed in which the power semiconductor device and the semiconductor device controlling the power device are formed in the same substrate but are completely isolated from each other.

Abstract translation: 公开了一种半导体器件，其包括基板，形成在基板中或基板的主表面上的预定区域处的绝缘膜，形成在至少绝缘膜上的多晶半导体层，形成在基板上的单晶半导体层 至少多晶半导体层，通过多晶半导体层形成为从单晶半导体层的顶部主表面延伸到至少绝缘膜的表面的隔离区，以将形成在单晶半导体中的部分电隔离 所述隔离区域与形成在所述单晶半导体层中的不被所述隔离区域包围的另一部分包围的至少一个半导体器件形成在由所述隔离区域包围的部分内。 该半导体器件具有另外的特征，即在基板的表面和单个硅谷半导体层上设置另一个使用基板的另一个主表面作为电极的半导体器件，并且多晶半导体层用于终止电力线 从衬底发出的，因此，安装在多晶半导体层上的单晶半导体层不受电力线的影响。 因此，可以获得能够有效地工作而不受基板中电位变化的影响的半导体器件，并且还可以形成智能型功率器件，其中功率半导体器件和控制功率器件的半导体器件 形成在相同的基板中，但彼此完全隔离。

公开(公告)号：US4924277A

公开(公告)日：1990-05-08

申请号：US342608

申请日：1989-04-20

Applicant: Hiroyuki Yamane ,  Yasushi Higuchi ,  Tetsuo Fujii

Inventor： Hiroyuki Yamane ,  Yasushi Higuchi ,  Tetsuo Fujii

IPC: H01L27/088 ,  H01L21/8234 ,  H01L27/092 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L27/0928 ,  H01L29/1045 ,  H01L29/1083 ,  H01L29/7836 ,  Y10S257/90

Abstract: In a MIS transistor device, a gate electrode is formed on a first conductivity-type well region formed in a semiconductor substrate. By implanting impurities with the gate electrode and an element-isolating region made up of a field insulating film as a mask, an N-type diffusion layer having a higher impurity concentration than the first conductivity-type well region is formed on the sides of the gate electrode. A second conductivity-type diffusion layer of a first impurity concentration higher than the N-type diffusion layer is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on one side of the gate electrode. A second conductivity-type diffusion layer of a second high concentration is formed with a smaller width than the N-type diffusion layer in the N-type diffusion layer formed on the other side of the gate electrode.

Abstract translation: 在MIS晶体管器件中，栅电极形成在形成于半导体衬底中的第一导电型阱区上。 通过将栅电极和由场绝缘膜构成的元件隔离区注入杂质作为掩模，在第二导电类型阱区的侧面上形成杂质浓度高于第一导电型阱区的N型扩散层 栅电极。 形成比N型扩散层高的第一杂质浓度的第二导电型扩散层的宽度小于形成在栅电极一侧的N型扩散层中的N型扩散层的宽度。 形成第二高浓度的第二导电型扩散层，其宽度小于形成在栅电极另一侧的N型扩散层中的N型扩散层的宽度。

公开(公告)号：US4393365A

公开(公告)日：1983-07-12

申请号：US279710

申请日：1981-07-02

Applicant: Nobuo Kondo ,  Masanori Naganoma ,  Hitoshi Hibi ,  Tetsuo Fujii ,  Kunihiko Suzuki

Inventor： Nobuo Kondo ,  Masanori Naganoma ,  Hitoshi Hibi ,  Tetsuo Fujii ,  Kunihiko Suzuki

IPC: G01D1/00 ,  B60R16/02 ,  B60R16/037 ,  F01P11/16 ,  G01D1/10 ,  G01D1/18 ,  G01D7/12 ,  G01K7/00 ,  G06F17/40 ,  B60Q5/00

CPC classification number: B60R16/0373 ,  F01P11/16 ,  G01D1/10 ,  F01P2031/20 ,  F01P2031/22

Abstract: An automotive abnormality forecasting and warning method and system for issuing a voice and visual alarm when a signal representing the condition of an automotive inspection item exceeds a predetermined value, which comprise steps of calculating the cooling water temperature change rate in variable cycles, determining a calculation cycle corresponding to the detected water temperature and the calculated change rate from a memory storing the cooling water temperature, water-temperature-change rate and calculation cycle in a predetermined relation, judging whether the detected water temperature and the calculated change rate are in a predetermined water overheat region, and issuing a voice alarm on an overheating trend in response to more than a predetermined number of the judging operations.

Abstract translation: 一种用于在表示汽车检查项目的条件的信号超过预定值时发出语音和视觉报警的汽车异常预报和警告方法和系统，包括以可变周期计算冷却水温度变化率的步骤，确定计算 循环对应于检测到的水温和计算出的变化率，从存储冷却水温度，水温变化率和计算周期的存储器以预定关系，判断检测到的水温和计算出的变化率是否为预定的 水过热区域，并且响应于多于一个预定数量的判断操作，发出过热趋势的语音报警。