公开(公告)号：US07277381B2

公开(公告)日：2007-10-02

申请号：US10163175

申请日：2002-06-05

Applicant: Denis J. Mestdagh

Inventor： Denis J. Mestdagh

IPC: H04J11/00

CPC classification number: H04B3/542 ,  H04B2203/5416 ,  H04B2203/5445 ,  H04B2203/5454 ,  H04L5/023 ,  H04L27/2607

Abstract: A method for transmitting data between at least three nodes of an orthogonal frequency-division multiplexing network, including assigning to each node at least one transmit frequency and one receive frequency, the assigned frequencies being different from one node to the other; forming data symbols to be transmitted all having the same duration whatever the transmission node; and adding, to each transmitted symbol, a cyclic prefix and a cyclic suffix reproducing a predetermined number of samples, respectively of the end and of the beginning of the symbol.

Abstract translation: 一种用于在正交频分复用网络的至少三个节点之间传送数据的方法，包括向每个节点分配至少一个发射频率和一个接收频率，所分配的频率不同于一个节点; 形成要传输的数据符号，具有相同的持续时间，无论传输节点如何; 并且向每个发送的符号添加循环前缀和循环后缀，分别再现符号的结尾和开头的预定数量的采样。

公开(公告)号：US20070222018A1

公开(公告)日：2007-09-27

申请号：US11713543

申请日：2007-03-02

Applicant: Patrick Poveda

Inventor： Patrick Poveda

IPC: H01L27/00

CPC classification number: H01L29/402 ,  H01L29/407 ,  H01L29/66143 ,  H01L29/806 ,  H01L29/872 ,  H01L29/8725

Abstract: A method for forming a component of TMBS type having its periphery formed of a trench with insulated walls filled with a conductor, including the steps of depositing on a semiconductor substrate a thick layer of a first insulating material and a thin layer of a second material; simultaneously digging a peripheral trench and the trenches of the component; isotropically etching the first material so that a cap overhanging a recess remains; forming a thin insulating layer; and filling the trenches and said recess with a conductive material.

Abstract translation: 一种用于形成其外围由填充有导体的绝缘壁形成沟槽的TMBS型的部件的方法，包括以下步骤：在半导体衬底上沉积厚层的第一绝缘材料和第二材料的薄层; 同时挖掘周边沟槽和部件的沟槽; 各向同性蚀刻第一材料，使得悬挂在凹部上的盖保留; 形成薄的绝缘层; 并用导电材料填充沟槽和凹槽。

公开(公告)号：US07275077B2

公开(公告)日：2007-09-25

申请号：US10395041

申请日：2003-03-21

Applicant: Pascal Moniot ,  David Furodet

Inventor： Pascal Moniot ,  David Furodet

IPC: G06F15/16 ,  G06F9/26 ,  H04L12/28

CPC classification number: H04L61/6022 ,  H04L29/12009 ,  H04L29/12801 ,  H04L29/12839 ,  H04L61/6004

Abstract: A method for associating with a first address a second address of reduced size, comprising: calculating a first intermediary address by the first address, the first intermediary address having a reduced size with respect to the first address; then choosing as a second address the first intermediary address if this second address is not associated with another first address, or, otherwise, calculating a second intermediary address by a first polynomial division of the first address, the second intermediary address having a reduced size as compared to the first address; then choosing as a second address the second intermediary address.

Abstract translation: 一种用于将缩小尺寸的第二地址与第一地址相关联的方法，包括：通过所述第一地址计算第一中间地址，所述第一中间地址相对于所述第一地址具有减小的大小; 然后如果该第二地址不与另一个第一地址相关联，则选择第二地址作为第二中间地址，否则，通过第一地址的第一多项式除法来计算第二中间地址，第二中间地址的大小减小为 与第一个地址相比; 然后选择第二个地址作为第二个中间地址。

公开(公告)号：US20070215909A1

公开(公告)日：2007-09-20

申请号：US11713903

申请日：2007-03-05

Applicant: Arnaud Tournier ,  Francois Roy

Inventor： Arnaud Tournier ,  Francois Roy

IPC: H01L29/76

CPC classification number: H01L27/14689 ,  H01L27/14601 ,  H01L27/1463 ,  H01L27/14654

Abstract: A pixel having a MOS-type transistor formed in and above a semiconductor substrate of a first doping type, a buried semiconductor layer of a second doping type being placed in the substrate under the MOS transistor and separated therefrom by a substrate portion forming a well. The buried semiconductor layer comprises a thin portion forming a pinch area placed under the transistor channel area and a thick portion placed under all or part of the source/drain areas of the transistor.

Abstract translation: 形成在第一掺杂型半导体衬底中和上方的MOS型晶体管的像素，第二掺杂类型的掩埋半导体层被放置在MOS晶体管下方的衬底中，并由形成阱的衬底部分分离。 掩埋半导体层包括形成位于晶体管沟道区域下方的夹紧区域的薄部分和放置在晶体管的源极/漏极区域全部或部分之下的厚部分。

公开(公告)号：US20070204085A1

公开(公告)日：2007-08-30

申请号：US11405269

申请日：2006-04-17

Applicant: William Orlando ,  Christian Schwarz

Inventor： William Orlando ,  Christian Schwarz

IPC: G06F13/24

CPC classification number: G06F21/74

Abstract: A method of processing interrupts in a processor adapted for operating either in a first mode, or in a second mode, and having at least one counter comprises the following, when an interrupt associated with an interrupt subroutine executable in the second mode is dispatched to the processor in the course of the execution of a process by the said processor in the first mode, at least the counter is initialized to a start value; then the counter is started while the processor is toggled into the second mode to execute the interrupt subroutine associated with the interrupt; when the counter reaches an end value, the processor is returned to the first mode for the continuation of the execution of the process.

Abstract translation: 一种处理器中的处理器的处理器，适于在第一模式或第二模式中操作，并具有至少一个计数器，包括以下步骤：当与第二模式中可执行的中断子程序相关联的中断被分派到 处理器在所述第一模式下由所述处理器执行处理的过程中，至少所述计数器被初始化为起始值; 那么当处理器切换到第二模式时，计数器开始执行与中断相关联的中断子程序; 当计数器达到结束值时，处理器返回到第一模式以继续执行该过程。

公开(公告)号：US20070201278A1

公开(公告)日：2007-08-30

申请号：US11742334

申请日：2007-04-30

Applicant: Jean Devin

Inventor： Jean Devin

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/06

CPC classification number: G11C16/3454 ,  G11C16/10

Abstract: The present invention relates to a method for programming a memory cell having a determined transconductance curve. The programming of the memory cell comprises a series of programming cycles each comprising a step of verifying the state of the memory cell. According to the present invention, the verify step comprises a first read of the memory cell with a first read voltage greater than a reference threshold voltage, and a second read of the memory cell with a second read voltage lower than or equal to the reference threshold voltage. The memory cell is considered not to be in the programmed state if first- and second-read currents flowing through the memory cell are above determined thresholds, and programming voltage pulses are applied to the memory cell while the latter is not in the programmed state. Application in particular to the programming of Flash memory cells.

Abstract translation: 本发明涉及一种用于对具有确定的跨导曲线的存储单元进行编程的方法。 存储器单元的编程包括一系列编程周期，每个编程周期包括验证存储器单元的状态的步骤。 根据本发明，验证步骤包括具有大于参考阈值电压的第一读取电压的存储器单元的第一次读取，以及具有低于或等于参考阈值的第二读取电压的存储器单元的第二次读取 电压。 如果流过存储单元的第一和第二读取电流高于确定的阈值，则存储单元被认为不处于编程状态，并且编程电压脉冲被施加到存储单元而后者不处于编程状态。 特别适用于闪存单元的编程。

公开(公告)号：US20070190787A1

公开(公告)日：2007-08-16

申请号：US11704799

申请日：2007-02-09

Applicant: Nicholas Loubet ,  Didier Dutartre ,  Alexandre Talbot ,  Laurent Rubaldo

Inventor： Nicholas Loubet ,  Didier Dutartre ,  Alexandre Talbot ,  Laurent Rubaldo

IPC: H01L21/302

CPC classification number: H01L21/306 ,  H01L21/3065

Abstract: A method for selectively etching single-crystal silicon-germanium in the presence of single-crystal silicon, including a chemical etch based on hydrochloric acid in gaseous phase at a temperature lower than approximately 700° C.

Abstract translation: 在单晶硅存在下选择性蚀刻单晶硅锗的方法，包括在低于大约700℃的温度下在气相中基于盐酸的化学蚀刻。

公开(公告)号：US20070188228A1

公开(公告)日：2007-08-16

申请号：US11621488

申请日：2007-01-09

Applicant: Claude Renous

Inventor： Claude Renous

IPC: H03F3/45

CPC classification number: G05F1/575

Abstract: A voltage regulation circuit intended to generate a regulated voltage for an electronic device, comprising: a transconductance amplifier based on a pair of MOS type differential amplifiers, said amplifier having a first input onto which a reference potential is applied and a second input onto which a counter reaction of said regulated voltage is input; a follower stage connected to the output from said transconductance amplifier; a MOS type transistor that will be used to make the output stage of the regulation circuit with a source connected to a first power supply potential. The transconductance amplifier comprises a resistive load 360 with a profile in K/gm, where gm is the transconductance coefficient of said input differential pair, said resistive load being connected to said first power supply potential.

Abstract translation: 一种旨在为电子设备产生调节电压的电压调节电路，包括：基于一对MOS型差分放大器的跨导放大器，所述放大器具有施加基准电位的第一输入端和第二输入端， 输入所述调节电压的反作用; 连接到所述跨导放大器的输出的跟随器级; 将用于使源极连接到第一电源电位的调节电路的输出级的MOS型晶体管。 跨导放大器包括具有K / gm的轮廓的电阻负载360，其中gm是所述输入差分对的跨导系数，所述电阻负载连接到所述第一电源电位。

公开(公告)号：US20070186030A1

公开(公告)日：2007-08-09

申请号：US11594689

申请日：2006-11-08

Applicant: Michel Harrand ,  Joseph Bulone

Inventor： Michel Harrand ,  Joseph Bulone

IPC: G06F12/06 ,  G06F12/00

CPC classification number: G11C11/40618 ,  G11C7/1006 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C8/12 ,  G11C11/406 ,  G11C11/4076 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096

Abstract: A method of fast random access management of a DRAM-type memory, including the steps of: dividing the memory into memory banks accessible independently in read and write mode; identifying the address of the bank concerned by a current request; comparing the address of the bank concerned by a current request with the addresses of the N−1 banks previously required, N being an integral number of cycles necessary to the executing of a request; and if the address of the bank concerned by a current request is equal to the address of a bank corresponding to one of the N−1 previous requests, suspending and memorizing the current request until the previous request involving the same bank is executed, otherwise, executing it.

Abstract translation: 一种DRAM型存储器的快速随机存取管理方法，包括以下步骤：将存储器分成以读和写模式独立访问的存储器组; 通过当前请求确定相关银行的地址; 将当前请求的有关银行的地址与先前需要的N-1个库的地址进行比较，N是执行请求所需的周期的整数; 并且如果当前请求所关联的银行的地址等于对应于N-1个先前请求之一的银行的地址，则暂停和存储当前请求直到执行涉及相同银行的先前请求为止，否则， 执行它

公开(公告)号：US07251673B2

公开(公告)日：2007-07-31

申请号：US10400811

申请日：2003-03-27

Applicant: William Orlando ,  Sophie Gabriele

Inventor： William Orlando ,  Sophie Gabriele

IPC: G06F7/52

CPC classification number: G06F7/535 ,  G06F2207/5354

Abstract: A method of automatic calculation of several integer divisions by a same integer divider, of several successive integer dividends, separated from one another by a constant iteration step, smaller than or equal to the divider, including selecting, from a table of increments, according to an iteration index, a 0 or a 1 to be added to the operation result of the preceding iteration, the number of 0s in the table of increments being equal to the divider minus 1.

Abstract translation: 一种通过相同的整数分频器自动计算几个整数除法的方法，该整数除数器通过恒定迭代步骤彼此分开的几个连续的整数除数，小于或等于分频器，包括从增量表中选择根据 迭代索引，0或1被添加到前一次迭代的操作结果中，增量表中的0的数目等于分频器减1。