公开(公告)号：US20250005138A1

公开(公告)日：2025-01-02

申请号：US18346222

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： Michael LeMay ,  David M. Durham

IPC: G06F21/54 ,  G06F21/78

Abstract: Techniques for explicit integrity check value initialization are described. In an embodiment, an apparatus includes an instruction decoder to decode a single instruction to set an integrity check value ICV corresponding to a destination location in a memory; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the single instruction, including storing data indicated by the single instruction into the destination location, and storing the ICV in the memory.

公开(公告)号：US20250005137A1

公开(公告)日：2025-01-02

申请号：US18346220

申请日：2023-07-01

Applicant: Intel Corporation

Inventor： David M. Durham

IPC: G06F21/54 ,  G06F21/55

Abstract: Techniques for instruction tagging for intra-object memory tagging are described. In an embodiment, an apparatus includes an instruction decoder to decode a first instruction having an instruction tag value; and execution circuitry coupled to the instruction decoder, the execution circuitry to perform one or more operations corresponding to the first instruction, including generating a first data tag value based on the instruction tag value and a relative enumeration in a pointer to data.

公开(公告)号：US20250004878A1

公开(公告)日：2025-01-02

申请号：US18539380

申请日：2023-12-14

Applicant: Intel Corporation

Inventor： Yanxin ZHAO ,  Tao XU ,  Yufu LI ,  Shijie LIU ,  Lei ZHU

IPC: G06F11/10

Abstract: A method and system for error check and scrub (ECS) error data collection and reporting for a memory device. A controller includes circuitry and a buffer. The circuitry may be configured to read ECS error data from a register of a memory device and calculate an ECS error increase rate based on the ECS error data. The circuitry may be configured to inform basic input output system (BIOS) by interrupt if a total number of ECS errors reaches or exceeds an ECS error number threshold or if the ECS error increase rate reaches or exceeds an ECS error rate threshold. The controller may be an out-of-band device, e.g., a baseboard management controller or a memory micro controller.

公开(公告)号：US20250004829A1

公开(公告)日：2025-01-02

申请号：US18345280

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Jeroen Leijten

IPC: G06F9/48

Abstract: Techniques for hardware based acceleration of synchronous data flow graphs for data-driven multi-core signal processing systems are described. In certain examples, a system includes a processor comprising a processing circuit to perform a task of a synchronous data flow graph, an input memory for the task of the synchronous data flow graph, an output memory for the task of the synchronous data flow graph, and a synchronous data flow manager circuit to store user-visible state for the input memory and the output memory; and a synchronous data flow functional circuit, coupled to the processor, to cause the processing circuit to perform the task based on the user-visible state from the synchronous data flow manager circuit.

公开(公告)号：US20250004775A1

公开(公告)日：2025-01-02

申请号：US18345909

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Zeshan Chishti ,  Jeffrey Cook ,  Thomas McDonald

IPC: G06F9/38

Abstract: Systems, methods, and apparatuses relating to hardware for auto-predication for loops with dynamically varying iteration counts are disclosed. In an embodiment, a processor core includes a decoder to decode instructions into decoded instructions, an execution unit to execute the decoded instructions, a branch predictor circuit to predict a future outcome of a branch instruction, and a branch predication manager circuit to identify a plurality of popular iteration counts for a loop and to predicate a region including a number of loop iterations equal to one of the plurality of popular iteration counts.

公开(公告)号：US20250004773A1

公开(公告)日：2025-01-02

申请号：US18217428

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Christopher J. HUGHES ,  Zhe WANG ,  Dan BAUM ,  Venkateswara Rao MADDURI ,  Chen DAN ,  Joseph NUZMAN

IPC: G06F9/38 ,  G06F9/30

Abstract: An apparatus and method are described for prefetching data with hints. For example, one embodiment of a processor comprises: a plurality of cores to process instructions; a first core of the plurality of cores comprising: decoder circuitry to decode instructions indicating memory operations including load operations of a first type with shared data hints and load operations of a second type without shared data hints; execution circuitry to execute the instructions to perform the memory operations; data prefetch circuitry to store tracking data in a tracking data structure responsive to the memory operations, a portion of the tracking data associated with the first type of load operations; and the data prefetch circuitry to detect memory access patterns using the tracking data, the data prefetch circuitry to responsively issue one or more prefetch operations using shared data hints based, at least in part, on the portion of the tracking data associated with the first type of load operations.

公开(公告)号：US20250004220A1

公开(公告)日：2025-01-02

申请号：US18346039

申请日：2023-06-30

Applicant: Intel Corporation

Inventor： Sufi R. Ahmed ,  Shan Zhong ,  Eric J. M. Moret ,  Yang Wu

IPC: G02B6/42

Abstract: Photonic integrated circuits and optical couplers with improved process tolerance, and methods of forming the same, are disclosed herein. In one example, an integrated circuit package includes a photonic integrated circuit (PIC) to send or receive optical signals and an optical coupler to optically couple the PIC to one or more optical fibers. The PIC includes a first interface with at least two recesses and one or more grooves positioned between the recesses, and the optical coupler includes a second interface with at least two protrusions and one or more ridges positioned between the protrusions (or vice versa). The protrusions on the optical coupler are mated with the recesses on the PIC, and the ridges on the optical coupler are mated with the grooves on the PIC.

公开(公告)号：US20250004206A1

公开(公告)日：2025-01-02

申请号：US18343175

申请日：2023-06-28

Applicant: Intel Corporation

Inventor： Chia-Pin Chiu ,  Tim T. Hoang ,  Kaveh Hosseini ,  Omkar G. Karhade

IPC: G02B6/30 ,  G02B6/42

Abstract: In one embodiment, an integrated circuit package includes a first (top) package substrate, a photonics integrated circuit (PIC) die coupled to the first package substrate, and a second package substrate coupled to a bottom side of the first package substrate. The package further includes a pedestal coupled to a top side of the second package substrate in an area of the second package substrate that extends beyond an edge of the first package substrate at which the PIC die is located.

公开(公告)号：US20250004121A1

公开(公告)日：2025-01-02

申请号：US18885758

申请日：2024-09-16

Applicant: INTEL CORPORATION

Inventor： Arnaud AMADJIKPE ,  Timo Sakari HUUSARI ,  Tae Young YANG ,  Hossein ALAVI ,  Steven CALLENDER ,  Bradley JACKSON ,  Ofer MARKISH ,  Woorim SHIN ,  Shengbo XU ,  Zhen ZHOU ,  Wei QIAN ,  Mengyuan HUANG

IPC: G01S13/42 ,  G01S7/35 ,  G01S13/89

Abstract: Disclosed herein is a lens antenna system that includes a reconfigurable aperture configured to receive a source beam. The reconfigurable aperture also provides an output beam based on a surface impedance distribution of the reconfigurable aperture and the received source beam. The control device is operatively coupled to the reconfigurable aperture, wherein the control device is configured to control the surface impedance distribution of the reconfigurable aperture to configure and reconfigure a beam pattern of the output beam. A plurality of antenna elements may be physically positioned proximate the reconfigurable aperture, wherein the plurality of antennas may be configured to generate the source beam.

公开(公告)号：US20250004035A1

公开(公告)日：2025-01-02

申请号：US18343763

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Krzysztof DOMANSKI ,  Manhar MUDDU

IPC: G01R31/26

Abstract: A non-transitory computer readable medium is provided. The non-transitory computer readable medium having instructions stored therein that when executed by a processor cause the processor to: receive current information of a semiconductor device, calculate an absolute current value of the semiconductor device from the current information and compare the absolute current value with a first threshold; receive information regarding a duration of a forward bias of the semiconductor device and compare the duration with a second threshold if the absolute current value is more than the first threshold; perform a layout review of tap spacing of selected semiconductor device components; and output safe operation area (SOA) information indicating a forward bias junction result based on the absolute current value, the duration of forward bias and the layout review.