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    Bone graft and scaffolding materials immobilized with type I collagen binding peptides
    182.
    发明授权
    Bone graft and scaffolding materials immobilized with type I collagen binding peptides 有权
    用I型胶原结合肽固定的骨移植物和脚手架材料

    公开(公告)号：US08349804B2

    公开(公告)日：2013-01-08

    申请号：US12278009

    申请日：2007-01-19

    Applicant: Yoon-Jeong Park ,  Chong-Pyoung Chung ,  Seung-Jin Lee ,  Jue-Yeon Lee

    Inventor： Yoon-Jeong Park ,  Chong-Pyoung Chung ,  Seung-Jin Lee ,  Jue-Yeon Lee

    IPC: A61K38/10 ,  A61K38/16

    CPC classification number: A61L27/10 ,  A61L27/34 ,  A61L27/54 ,  A61L2430/02

    Abstract: The present invention relates to a pharmaceutical composition comprising a bone graft material, a scaffold for tissue engineering applications and type I collagen Binding Peptides which have bone calcification-promoting peptides immobilized on the surface, and more particularly, to a bone graft material and a scaffold for tissue engineering applications (hereinafter, referred to as scaffold), which have peptides specifically binding with type I collagen immobilized on the surface, and pharmaceutical composition for recovering tissue regeneration containing type I collagen binding-inducing peptide. In the inventive bone graft material and scaffold for tissue engineering applications, the cells related to regeneration by collagen binding-inducing peptide adhered to the surface, promote an adhesion of type I collagen binding-inducing peptide (main ingredients of extracellular matrix) to increase differentiation rate into bone tissues, and promote a calcification which is last step of bone regeneration to maximize a tissue regeneration finally.

    Abstract translation: 本发明涉及一种药物组合物，其包含骨移植材料，用于组织工程应用的支架和具有固定在表面上的骨钙化促进肽的I型胶原结合肽，更具体地涉及骨移植材料和支架 用于组织工程应用（以下称为支架），其具有与固定在表面上的I型胶原特异性结合的肽，以及用于回收含有I型胶原结合诱导肽的组织再生的药物组合物。 在用于组织工程应用的本发明的骨移植物材料和支架中，与通过胶原结合诱导肽再生的细胞粘附到表面上，促进I型胶原结合诱导肽（细胞外基质的主要成分）的粘附以增加分化 进入骨组织，并促进钙化，这是骨再生的最后一步，最终最大限度地发挥组织再生。

    Bottle cap
    183.
    外观设计
    Bottle cap 有权

    公开(公告)号：USD673449S1

    公开(公告)日：2013-01-01

    申请号：US29396906

    申请日：2011-07-08

    Applicant: Hye Jin Lee

    Designer： Hye Jin Lee

    Method and apparatus for supporting co-located coexistence mode
    185.
    发明授权
    Method and apparatus for supporting co-located coexistence mode 有权
    支持共同共存模式的方法和装置

    公开(公告)号：US08345634B2

    公开(公告)日：2013-01-01

    申请号：US12772033

    申请日：2010-04-30

    Applicant: Jin Lee ,  Yong Ho Kim ,  Ki Seon Ryu

    Inventor： Jin Lee ,  Yong Ho Kim ,  Ki Seon Ryu

    IPC: H04Q7/00

    CPC classification number: H04W88/00 ,  H04W16/14 ,  H04W36/0033 ,  H04W36/0077

    Abstract: A method and apparatus for reducing interference between systems when a plurality of wireless access systems are co-located are disclosed. To support CLC mode, an MS in the CRC mode transmits a handover request message to a first Base Station (BS) to initiate a handover process, receives a handover command message acknowledging the handover request message from the first BS, transmits a ranging request message to second BS at network reentry after handover, and receives from the second BS a ranging response message including CRC start time information that set by the second BS.

    Abstract translation: 公开了一种用于在多个无线接入系统共同定位时减少系统之间的干扰的方法和装置。 为了支持CLC模式，CRC模式的MS向第一基站（BS）发送切换请求消息以发起切换过程，从第一BS接收确认切换请求消息的切换命令消息，发送测距请求消息 在切换之后进行网络再入的第二BS，并且从第二BS接收包括由第二BS设置的CRC开始时间信息的测距响应消息。

    Resistive memory device and method for fabricating the same
    186.
    发明授权
    Resistive memory device and method for fabricating the same 有权
    电阻式存储器件及其制造方法

    公开(公告)号：US08345463B2

    公开(公告)日：2013-01-01

    申请号：US12411455

    申请日：2009-03-26

    Applicant: Yu-Jin Lee ,  Yun-Taek Hwang

    Inventor： Yu-Jin Lee ,  Yun-Taek Hwang

    IPC: G11C11/00

    CPC classification number: H01L45/1233 ,  H01L45/04 ,  H01L45/1273 ,  H01L45/145 ,  H01L45/146 ,  H01L45/147 ,  H01L45/16

    Abstract: A resistive memory device includes: a bottom electrode formed over a substrate; and an insulation layer having a hole structure formed over the substrate structure. Herein, the hole structure exposes the bottom electrode, has sidewalls of positive slope, and has a bottom width equal to or smaller than a width of the bottom electrode; a resistive layer formed over the hole structure; and an upper electrode formed over the resistive layer.

    Abstract translation: 电阻式存储器件包括：形成在衬底上的底部电极; 以及在基板结构上形成有孔结构的绝缘层。 这里，孔结构暴露底部电极，具有正斜率的侧壁，并且底部宽度等于或小于底部电极的宽度; 形成在孔结构上的电阻层; 以及形成在电阻层上的上电极。

    Light emitting diode driving circuit and light emitting diode array device
    188.
    发明授权
    Light emitting diode driving circuit and light emitting diode array device 有权
    发光二极管驱动电路和发光二极管阵列器件

    公开(公告)号：US08339050B2

    公开(公告)日：2012-12-25

    申请号：US13209122

    申请日：2011-08-12

    Applicant: Young Jin Lee ,  Byoung Own Min ,  Gil Han Park ,  Grigory Onushkin

    Inventor： Young Jin Lee ,  Byoung Own Min ,  Gil Han Park ,  Grigory Onushkin

    IPC: H05B37/00

    CPC classification number: H05B33/0803 ,  H05B33/0821 ,  Y02B20/342 ,  Y10S362/80 ,  Y10S362/808

    Abstract: There is provided an LED driving circuit including: at least one ladder network circuit including: (n+1) number of first branches connected in parallel with one another by n number of first middle junction points between a first junction point and a second junction point, where n denotes an integer satisfying n≧2, (n+1) number of second branches connected in parallel with one another by n number of second middle junction points between the first junction point and the second junction point, the (n+1) number of second branches connected in parallel with the first branches; and n number of middle branches connecting the first and second middle junction points of an identical m sequence to each other, respectively, wherein each of the first and second, and middle branches comprises at least one LED device.

    Abstract translation: 提供了一种LED驱动电路，包括：至少一个梯形网络电路，包括：（n + 1）数个第一分支，其在第一连接点和第二连接点之间彼此并联连接n个第一中间连接点 ，其中n表示满足n≥2的整数，（n + 1）个在第一连接点和第二连接点之间由n个第二中间连接点彼此并联连接的第二分支数，第（n + 1）个 ）与第一分支并联连接的第二分支的数量; 以及分别将相同m个序列的第一和第二中间连接点彼此连接的n个中间分支，其中第一和第二和中间分支中的每一个包括至少一个LED器件。

    SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF
    189.
    发明申请
    SEMICONDUCTOR MEMORY DEVICE AND DRIVING METHOD THEREOF 有权
    半导体存储器件及其驱动方法

    公开(公告)号：US20120314525A1

    公开(公告)日：2012-12-13

    申请号：US13564842

    申请日：2012-08-02

    Applicant: Myoung-Jin LEE ,  Jin-Hong AN

    Inventor： Myoung-Jin LEE ,  Jin-Hong AN

    IPC: G11C8/08 ,  G11C8/00

    CPC classification number: G11C8/08 ,  G11C11/4076 ,  G11C11/4085

    Abstract: A semiconductor memory device includes a plurality of wordlines and a driver configured to, when an wordline of the plurality of wordlines is activated by an active command, drive at least one non-activated wordline neighboring the activated wordline and remaining non-activated wordlines with different wordline driving voltage levels during a period of time that the activated wordline is driven to a high voltage level.

    Abstract translation: 半导体存储器件包括多个字线和驱动器，其被配置为当多个字线的字线被激活命令激活时，驱动与激活的字线相邻的至少一个非激活字线和具有不同的剩余非激活字线 在激活的字线被驱动到高电压电平的时间段内的字线驱动电压电平。

    METHODS OF OPERATING NON-VOLATILE MEMORY DEVICES DURING WRITE OPERATION INTERRUPTION, NON-VOLATILE MEMORY DEVICES, MEMORIES AND ELECTRONIC SYSTEMS OPERATING THE SAME
    190.
    发明申请
    METHODS OF OPERATING NON-VOLATILE MEMORY DEVICES DURING WRITE OPERATION INTERRUPTION, NON-VOLATILE MEMORY DEVICES, MEMORIES AND ELECTRONIC SYSTEMS OPERATING THE SAME 有权
    在写操作中断期间操作非易失性存储器件的方法，非易失性存储器件，存储器和操作其的电子系统

    公开(公告)号：US20120311407A1

    公开(公告)日：2012-12-06

    申请号：US13193191

    申请日：2011-07-28

    Applicant: Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

    Inventor： Kwang Jin Lee ,  Yeong Taek Lee ,  Woo Yeong Cho ,  Hoi Ju Chung

    IPC: H03M13/05 ,  G06F11/10

    CPC classification number: G06F11/1048

    Abstract: A non-volatile memory device may operate by writing a portion of a new codeword to an address in the device that stores an old codeword, as part of a write operation. An interruption of the write operation can be detected before completion, which indicates that the address stores the portion of the new codeword and a portion of the old codeword. The portion of the old codeword can be combined with the portion of the new codeword to provide an updated codeword. Error correction bits can be generated using the updated codeword and the error correction bits can be written to the address.

    Abstract translation: 作为写入操作的一部分，非易失性存储器件可以通过将新的码字的一部分写入存储旧码字的设备中的地址来操作。 可以在完成之前检测写入操作的中断，这指示该地址存储新码字的一部分和旧码字的一部分。 旧码字的部分可以与新码字的部分组合以提供更新的码字。 可以使用更新的码字生成纠错位，并且可以将错误校正位写入地址。

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