公开(公告)号：US07145828B2

公开(公告)日：2006-12-05

申请号：US11105169

申请日：2005-04-12

Applicant: Yun-Sang Lee ,  Jung-Bae Lee

Inventor： Yun-Sang Lee ,  Jung-Bae Lee

IPC: G11C7/00

CPC classification number: G11C11/40611 ,  G11C11/406 ,  G11C11/40618

Abstract: Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. When all bank addresses have been supplied for the current row, the SDRAM circuit updates the current refresh row and repeats the process. This process can allow a memory controller to modify an auto-refresh bank sequence as necessary such that auto-refresh operations can proceed on some memory banks concurrently with reads and writes to other memory banks, allowing better utilization of the SDRAM circuit. Other embodiments are described and claimed.

Abstract translation: 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 当所有存储体地址已被提供给当前行时，SDRAM电路更新当前刷新行并重复该过程。 该过程可以允许存储器控制器根据需要修改自动刷新存储体序列，使得自动刷新操作可以在一些存储体上与对其它存储体的读取和写入同时进行，从而更好地利用SDRAM电路。 描述和要求保护其他实施例。

公开(公告)号：US07034565B2

公开(公告)日：2006-04-25

申请号：US10716120

申请日：2003-11-18

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: H03K19/003

CPC classification number: G11C7/1057 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084

Abstract: Provided are an on-die termination (“ODT”) circuit and ODT method which are capable of minimizing consumption of an on-chip DC current, and a memory system which adopts a memory device having the same, where the ODT circuit includes a termination voltage port, a data input/output (“I/O”) port, a first termination resistor, a switch, and a termination enable signal generating circuit; the termination voltage port receives termination voltage from a voltage regulator or a memory controller which is installed outside the memory device; one end of the first termination resistor is connected to the data I/O port; the switch selectively connects the termination voltage port to the other end of the first termination resistor in response to a termination enable signal; the termination enable signal generating circuit generates the termination enable signal in response to a signal which indicates a valid section of input data or that the present period is not a read period during write operations of the memory device, and may also generate the termination enable signal in response to a signal output from a mode register set (“MRS”); and the ODT circuit may include a second termination resistor, one end of which is connected to the data I/O port and the other end of which is connected to the termination voltage port.

Abstract translation: 提供能够最小化片上直流电流的消耗的片上终端（“ODT”）电路和ODT方法，以及采用具有该片上直流电流的存储器件的存储器系统，其中ODT电路包括终端 电压端口，数据输入/输出（“I / O”）端口，第一终端电阻器，开关和终止使能信号发生电路; 终端电压端口从安装在存储装置外部的电压调节器或存储器控制器接收终端电压; 第一个终端电阻的一端连接到数据I / O端口; 所述开关响应于终止使能信号而选择性地将终端电压端口连接到第一终端电阻器的另一端; 终止使能信号发生电路响应于指示输入数据的有效部分的信号或当前周期不是存储器件的写入操作期间的读取周期而产生终止使能信号，并且还可以产生终止使能信号 响应于从模式寄存器组（“MRS”）输出的信号; 并且ODT电路可以包括第二终端电阻器，其一端连接到数据I / O端口，另一端连接到终端电压端口。

公开(公告)号：US20060083079A1

公开(公告)日：2006-04-20

申请号：US11252535

申请日：2005-10-18

Applicant: Sang-Joon Hwang ,  Dong-Jin Lee ,  Jung-Bae Lee

Inventor： Sang-Joon Hwang ,  Dong-Jin Lee ,  Jung-Bae Lee

IPC: G11C16/04

CPC classification number: G11C7/1051 ,  G11C5/147 ,  G11C7/1048 ,  G11C7/1057

Abstract: A data output buffer includes an output terminal, a buffer and a pull-down driver. The output terminal is coupled to a first end of a transmission line, the transmission line being coupled to a pull-up termination resistor at a second end. The buffer pulls up the output terminal to a first power supply voltage and pulls down the output terminal to a second power supply voltage based on an output data signal. The pull-down driver pre-emphasizes an initial stage of a pull-down driving operation of the output terminal based on the output data.

Abstract translation: 数据输出缓冲器包括输出端子，缓冲器和下拉驱动器。 输出端耦合到传输线的第一端，传输线在第二端耦合到上拉终端电阻。 缓冲器将输出端上拉至第一电源电压，并根据输出数据信号将输出端拉低至第二电源电压。 下拉驱动器基于输出数据预先强调输出端子的下拉驱动操作的初始阶段。

公开(公告)号：US20060018174A1

公开(公告)日：2006-01-26

申请号：US11169241

申请日：2005-06-27

Applicant: Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

Inventor： Taek-Seon Park ,  Yun-Sang Lee ,  Jung-Bae Lee

IPC: G11C7/00

CPC classification number: G11C11/406 ,  G11C11/40611 ,  G11C11/40618 ,  G11C2211/4067

Abstract: Method and apparatus for use with multi-bank Synchronous Dynamic Random Access Memory (SDRAM) circuits, modules, and memory systems are disclosed. In one described embodiment, an SDRAM circuit receives a bank address to be used in an auto-refresh operation, and performs the auto-refresh operation on the specified bank and for a current refresh row. The device is allowed to enter a self-refresh mode before auto-refresh operations have been completed for all banks and the current refresh row. The memory device completes refresh operations for the current refresh row before proceeding to perform self-refresh operations for new rows. Other embodiments are described and claimed.

Abstract translation: 公开了用于多存储体同步动态随机存取存储器（SDRAM）电路，模块和存储器系统的方法和装置。 在一个描述的实施例中，SDRAM电路接收要在自动刷新操作中使用的存储体地址，并对指定的存储体和当前刷新行执行自动刷新操作。 在所有存储区和当前刷新行完成自动刷新操作之前，允许该设备进入自刷新模式。 在继续对新行执行自刷新操作之前，内存设备完成当前刷新行的刷新操作。 描述和要求保护其他实施例。

公开(公告)号：US06983010B1

公开(公告)日：2006-01-03

申请号：US09542042

申请日：2000-03-31

Applicant: Jae-yoon Sim ,  Hong-joon Park ,  Soo-in Cho ,  Jung-bae Lee

Inventor： Jae-yoon Sim ,  Hong-joon Park ,  Soo-in Cho ,  Jung-bae Lee

IPC: H03H7/30

CPC classification number: G11C7/1057 ,  G11C7/1012 ,  G11C7/1051 ,  G11C7/22 ,  G11C7/222 ,  H01L27/088 ,  H04L27/01

Abstract: A high frequency equalizer using a demultiplexing technique and a semiconductor device using the same are provided. The high frequency equalizer demultiplexes input data input through an input and output terminal into a plurality of input data items, each having a time difference that is the same as the period of the input data. The equalizer restores the lost high frequency data components of the plurality of demultiplexed input data items, multiplexes the restored plurality of data items, and sequentially outputs the restored data items one by one. Therefore, using this high frequency equalizer, it is possible to allow enough time to restore the lost high frequency component even though the period of the input data is reduced by an increase of the data transmission speed. Using this high frequency equalizer, it is possible to correctly restore the lost high frequency component even at a high data transmission speed. Therefore, according to the semiconductor device including the high frequency equalizer, the lost high frequency component of data can be restored even at a high data transmission speed.

Abstract translation: 提供了使用解复用技术的高频均衡器和使用其的半导体器件。 高频均衡器将通过输入和输出端输入的输入数据解复用为多个输入数据项，每个具有与输入数据周期相同的时间差。 均衡器恢复多路复用输入数据项的丢失的高频数据分量，复用恢复的多个数据项，并逐个依次输出恢复的数据项。 因此，即使通过数据传输速度的增加来减少输入数据的周期，也可以使用这种高频均衡器来允许足够的时间来恢复丢失的高频分量。 使用该高频均衡器，即使在高数据传输速度下也可以正确地恢复丢失的高频分量。 因此，根据包括高频均衡器的半导体器件，即使在高数据传输速度下也可以恢复数据的丢失高频分量。

公开(公告)号：US06965528B2

公开(公告)日：2005-11-15

申请号：US10641637

申请日：2003-08-14

Applicant: Jae-Hyeong Lee ,  Jung-Bae Lee ,  Dong-Yang Lee

Inventor： Jae-Hyeong Lee ,  Jung-Bae Lee ,  Dong-Yang Lee

IPC: G11C7/00 ,  G06F13/16 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076

CPC classification number: G11C11/4076 ,  G06F13/1647 ,  G11C7/1045 ,  G11C7/22 ,  G11C2207/2281 ,  G11C2207/229

Abstract: A memory device having a high bus efficiency on a network, an operating method of the memory device, and a memory system including the memory device are provided. The memory device includes banks, a programming register, and a controller. Each of the banks has a plurality of memory cells arranged in a matrix of rows and columns. In a write operation, the programming register stores simultaneous write information on how many banks there are in which data are stored. In a read operation, the controller selects one of the banks subjected to the write operation in response to the simultaneous write information to read out the memory cell data in the selected bank.

Abstract translation: 提供了一种在网络上具有高总线效率的存储器件，存储器件的操作方法以及包括存储器件的存储器系统。 存储器件包括存储体，编程寄存器和控制器。 每个存储体具有以行和列的矩阵排列的多个存储单元。 在写入操作中，编程寄存器存储关于存储了哪些数据的存储器的同时写入信息。 在读取操作中，控制器响应于同时写入信息来选择经过写入操作的存储体之一，以读出所选择的存储体中的存储器单元数据。

公开(公告)号：US20050210175A1

公开(公告)日：2005-09-22

申请号：US11024860

申请日：2004-12-30

Applicant: Jung-bae Lee

Inventor： Jung-bae Lee

IPC: G11C8/06 ,  G06F13/14 ,  G11C5/00 ,  G11C5/06 ,  G11C7/10 ,  G11C11/409

CPC classification number: G11C5/00 ,  G11C5/06 ,  G11C7/1048 ,  G11C11/409 ,  H05K1/0246

Abstract: A memory module and a related memory system are disclosed. The memory module comprises a semiconductor memory having a data output buffer, a data input buffer, a command/address input buffer and a first termination resistor unit connected to a data bus. The memory module further comprises a second termination resistor unit connected to an internal command/address bus. First and second termination resistor units are preferably of different resistive value and/or type.

Abstract translation: 公开了一种存储器模块和相关存储器系统。 存储器模块包括具有数据输出缓冲器，数据输入缓冲器，连接到数据总线的命令/地址输入缓冲器和第一终端电阻器单元的半导体存储器。 存储器模块还包括连接到内部命令/地址总线的第二终端电阻器单元。 第一和第二终端电阻器单元优选地具有不同的电阻值和/或类型。

公开(公告)号：US20050024984A1

公开(公告)日：2005-02-03

申请号：US10771488

申请日：2004-02-02

Applicant: Jung-bae Lee ,  One-gyun La

Inventor： Jung-bae Lee ,  One-gyun La

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/409 ,  G11C8/00

CPC classification number: G11C7/1093 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/1078 ,  G11C7/1087

Abstract: A circuit for receiving data to be written in a synchronous semiconductor memory device, comprising: a first set of latches for receiving an n-bit data upon transition of an internal strobe signal; a counter for counting the number of transitions of the internal strobe signal and for outputting an indicating signal upon counting the end of a string of internal strobe signals; a second set of latches for receiving the outputs of the first set of latches, the second set of latches being clocked by the indicating signal; and a third set of latches for receiving the outputs of the second set of latches, the third set of latches being clocked by a clock signal derived from a system clock.

Abstract translation: 一种用于接收要写入同步半导体存储器件的数据的电路，包括：第一组锁存器，用于在内部选通信号转换时接收n位数据; 计数器，用于对内部选通信号的转换次数进行计数，并在计数一串内部选通信号的结束时输出指示信号; 第二组锁存器，用于接收第一组锁存器的输出，第二组锁存器由指示信号计时; 以及第三组锁存器，用于接收第二组锁存器的输出，第三组锁存器由从系统时钟导出的时钟信号计时。

公开(公告)号：US06826115B2

公开(公告)日：2004-11-30

申请号：US10640146

申请日：2003-08-13

Applicant: Jung-Bae Lee ,  Yun-Sang Lee

Inventor： Jung-Bae Lee ,  Yun-Sang Lee

IPC: G11C800

CPC classification number: G11C7/1021 ,  G11C8/10 ,  G11C8/12

Abstract: A semiconductor memory device having a partial activation framework, which provides an efficient page mode operation while operating in a partial activation mode. Control circuits and methods are provided to enable a page mode operation (for read and write data accesses) in a semiconductor memory device (such as a DRAM, FCRAM) having a partial activation framework, resulting in an improved data access speed when data is written/read from memory locations having the same wordline address. In one aspect, a method for accessing data in a memory device comprises activating a first wordline corresponding to a first address to perform a data access operation, receiving a second address after the first address, if the second address is the same as the first address, generating a page mode enable signal for maintaining an activated state of the first wordline corresponding to the first address while activating a second wordline corresponding to the second address, and deactivating the first and second wordlines in response to disabling of the page mode enable signal.

公开(公告)号：US06754119B2

公开(公告)日：2004-06-22

申请号：US10002542

申请日：2001-11-13

Applicant: Chan Yong Lee ,  Jung Bae Lee ,  Won Seok Lee

Inventor： Chan Yong Lee ,  Jung Bae Lee ,  Won Seok Lee

IPC: G11C700

CPC classification number: G11C7/1069 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1096 ,  G11C7/12 ,  G11C2207/002

Abstract: A memory charging circuit includes a read charge control circuit controlled according to a read control signal and an address value. A write charge control circuit is controlled according to a write control signal and the same or a different address value. Charging to and charging from the same data IO lines is controlled using the read charge amplifier circuit and the write charge amplifier circuit. A column select line circuit can be configured into a first arrangement where a first output is activated according to a read control signal and an address and a second output is activated according to a write control signal and the same or a different address. In a second arrangement, the first output is activated according to an address and either the read control signal or the write control signal.

Abstract translation: 存储器充电电路包括根据读取控制信号和地址值控制的读取充电控制电路。 写入充电控制电路根据写入控制信号和相同或不同的地址值进行控制。 使用读取的电荷放大器电路和写入电荷放大器电路来控制对相同数据IO线的充电和充电。 列选择线路电路可以被配置成根据读控制信号和地址激活第一输出的第一布置，并且根据写控制信号和相同或不同的地址来激活第二输出。 在第二布置中，根据地址和读控制信号或写控制信号来激活第一输出。