公开(公告)号：US07459756B2

公开(公告)日：2008-12-02

申请号：US11467980

申请日：2006-08-29

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chuan-Yi Lin ,  Chenming Hu

IPC: H01L29/76

CPC classification number: H01L21/28052 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/458 ,  H01L29/4908 ,  H01L29/665 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78648

Abstract: Provided is a semiconductor device and a method for its fabrication. The device includes a semiconductor substrate, a first silicide in a first region of the substrate, and a second silicide in a second region of the substrate. The first silicide may differ from the second silicide. The first silicide and the second silicide may be an alloy silicide.

Abstract translation: 提供一种半导体器件及其制造方法。 该器件包括半导体衬底，衬底的第一区域中的第一硅化物和衬底的第二区域中的第二硅化物。 第一硅化物可能与第二硅化物不同。 第一硅化物和第二硅化物可以是合金硅化物。

公开(公告)号：US07453133B2

公开(公告)日：2008-11-18

申请号：US10880992

申请日：2004-06-30

Applicant: Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

Inventor： Wen-Chin Lee ,  Chung-Hu Ge ,  Chenming Hu

IPC: H01L27/095

CPC classification number: H01L23/3192 ,  H01L23/485 ,  H01L29/161 ,  H01L29/165 ,  H01L29/47 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/7834 ,  H01L2924/0002 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00

Abstract: A preferred embodiment of the present invention comprises a dielectric/metal/2nd energy bandgap (Eg) semiconductor/1st Eg substrate structure. In order to reduce the contact resistance, a semiconductor with a lower energy bandgap (2nd Eg) is put in contact with metal. The energy bandgap of the 2nd Eg semiconductor is lower than the energy bandgap of the 1st Eg semiconductor and preferably lower than 1.1eV. In addition, a layer of dielectric may be deposited on the metal. The dielectric layer has built-in stress to compensate for the stress in the metal, 2nd Eg semiconductor and 1st Eg substrate. A process of making the structure is also disclosed.

Abstract translation: 本发明的优选实施方案包括介电/金属/第二能带隙（E />）半导体/第一电极 g 衬底结构。 为了降低接触电阻，将具有较低能量带隙（2Ω）的半导体与金属接触。 第二个和第二个半导体的能带隙比第一个第二半导体的能量带隙低， 半导体，优选低于1.1eV。 此外，可以在金属上沉积介电层。 电介质层具有内置应力以补偿金属，第二和第二半导体中的应力， g 衬底。 还公开了制造该结构的过程。

公开(公告)号：US20080277735A1

公开(公告)日：2008-11-13

申请号：US11800615

申请日：2007-05-07

Applicant: Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Ta-Ming Kuan ,  Wen-Chin Lee

Inventor： Chih-Hsin Ko ,  Hung-Wei Chen ,  Chung-Hu Ke ,  Ta-Ming Kuan ,  Wen-Chin Lee

IPC: H01L29/417 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823814 ,  H01L21/823807 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7848

Abstract: A semiconductor structure includes a semiconductor substrate; a gate dielectric over the semiconductor substrate; a gate electrode over the gate dielectric; a deep source/drain region adjacent the gate electrode; a silicide region over the deep source/drain region; and an elevated metallized source/drain region between the silicide region and the gate electrode. The elevated metallized source/drain region adjoins the silicide region.

Abstract translation: 半导体结构包括半导体衬底; 半导体衬底上的栅极电介质; 位于栅极电介质上的栅电极; 与栅电极相邻的深源/漏区; 深源/漏区上的硅化物区; 以及在硅化物区域和栅电极之间的升高的金属化源极/漏极区域。 升高的金属化源极/漏极区域邻接硅化物区域。

公开(公告)号：US07429980B2

公开(公告)日：2008-09-30

申请号：US10991419

申请日：2004-11-19

Applicant: Wen-Chin Lee ,  Hsiang-Kuang Chen

Inventor： Wen-Chin Lee ,  Hsiang-Kuang Chen

IPC: G09G5/00 ,  G09G5/08 ,  G06F3/033 ,  G01B7/14 ,  G01B7/30 ,  G01R33/06 ,  H01L43/06

CPC classification number: G06F3/0383 ,  G01D5/145 ,  G06F3/0362

Abstract: An oscillation and rotation metric controller comprised of a scrolling wheel mechanism to oscillate for driving magnetic poles of a permanent magnet to displace thus to generate signals of changed magnetic field, signals being retrieved to achieve lateral oscillation metric control; and a knob switch encoder being fixed to the scrolling wheel mechanism to execute metric control by rotation displacement.

Abstract translation: 振荡和旋转度量控制器包括滚动轮机构，用于振荡以驱动永磁体的磁极，从而移位，从而产生改变的磁场的信号;检索信号以实现横向振荡度量控制; 以及旋钮开关编码器，其被固定到滚动轮机构，以通过旋转位移执行度量控制。

公开(公告)号：US20080145984A1

公开(公告)日：2008-06-19

申请号：US11640713

申请日：2006-12-18

Applicant: Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

Inventor： Chung-Hu Ke ,  Chih-Hsin Ko ,  Hung-Wei Chen ,  Wen-Chin Lee

IPC: H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/28052 ,  H01L21/28518 ,  H01L21/823814 ,  H01L29/4933 ,  H01L29/665 ,  H01L29/7843

Abstract: A method for forming a semiconductor structure includes: providing a semiconductor substrate; forming an NMOS device at a surface of the semiconductor substrate, which comprises forming a first source/drain electrode on a first source/drain region of the NMOS device, wherein the first source/drain electrode has a first barrier height; forming a PMOS device at the surface of the semiconductor substrate comprising forming a second source/drain electrode on a second source/drain region of the PMOS device, wherein the second source/drain electrode has a second barrier height, and wherein the first barrier height is different from the second barrier height; forming a first stressed film having a first intrinsic stress over the NMOS device; and forming a second stressed film having a second intrinsic stress over the PMOS device, wherein the first intrinsic stress is more tensile than the second intrinsic stress.

Abstract translation: 一种形成半导体结构的方法包括：提供半导体衬底; 在所述半导体衬底的表面上形成NMOS器件，其包括在所述NMOS器件的第一源极/漏极区域上形成第一源极/漏极，其中所述第一源极/漏极具有第一势垒高度; 在所述半导体衬底的表面上形成PMOS器件，包括在所述PMOS器件的第二源极/漏极区域上形成第二源极/漏极电极，其中所述第二源极/漏极具有第二势垒高度，并且其中所述第一势垒高度 与第二屏障高度不同; 在NMOS器件上形成具有第一固有应力的第一应力膜; 以及在所述PMOS器件上形成具有第二固有应力的第二应力膜，其中所述第一本征应力比所述第二固有应力更具拉伸力。

公开(公告)号：US07358571B2

公开(公告)日：2008-04-15

申请号：US10969374

申请日：2004-10-20

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chung-Hu Ke

IPC: H01L27/12

CPC classification number: H01L29/66772 ,  H01L27/1203 ,  H01L29/78618 ,  Y10S257/90

Abstract: A semiconductor device comprises a semiconductor mesa overlying a dielectric layer, a gate stack formed overlying the semiconductor mesa, and an isolation spacer formed surrounding the semiconductor mesa and filling any undercut region at edges of the semiconductor mesa.

Abstract translation: 半导体器件包括覆盖介电层的半导体台面，形成在半导体台面上的栅叠层，以及形成在半导体台面周围的隔离间隔物，并填充半导体台面的边缘处的任何底切区域。

公开(公告)号：US07355262B2

公开(公告)日：2008-04-08

申请号：US11378907

申请日：2006-03-17

Applicant: Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

Inventor： Chih-Hsin Ko ,  Wen-Chin Lee ,  Chung-Hu Ke ,  Hung-Wei Chen

IPC: H01L29/00 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113

CPC classification number: H01L21/76224 ,  H01L21/324 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823878 ,  H01L29/1037 ,  H01L29/66636 ,  H01L29/7834 ,  H01L29/7843 ,  H01L29/7848

Abstract: Semiconductor structures are formed using diffusion topography engineering (DTE). A preferred method includes providing a semiconductor substrate, forming trench isolation regions that define a diffusion region, performing a DTE in a hydrogen-containing ambient on the semiconductor substrate, and forming a MOS device in the diffusion region. The DTE causes silicon migration, forming a rounded or a T-shaped surface of the diffusion regions. The method may further include recessing a portion of the diffusion region before performing the DTE. The diffusion region has a slanted surface after performing the DTE.

Abstract translation: 半导体结构使用扩散地形工程（DTE）形成。 优选的方法包括提供半导体衬底，形成限定扩散区域的沟槽隔离区域，在半导体衬底上的含氢环境中进行DTE，以及在扩散区域中形成MOS器件。 DTE导致硅迁移，形成扩散区域的圆形或T形表面。 该方法还可以包括在执行DTE之前使扩散区的一部分凹陷。 在执行DTE之后，扩散区域具有倾斜表面。

公开(公告)号：US07342289B2

公开(公告)日：2008-03-11

申请号：US10637351

申请日：2003-08-08

Applicant: Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos H. Diaz ,  Fu-Liang Yang

Inventor： Chien-Chao Huang ,  Chung-Hu Ge ,  Wen-Chin Lee ,  Chenming Hu ,  Carlos H. Diaz ,  Fu-Liang Yang

IPC: H01L29/76

CPC classification number: H01L29/6659 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823828 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/7833 ,  H01L29/7842 ,  H01L29/7843

Abstract: A structure to improve carrier mobility of a MOS device in an integrated circuit. The structure comprises a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a conformal stress film covering the source region, the drain region, and the conductive gate. In addition, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a plurality of stress films covering the source region, the drain region, and the conductive gate. Moreover, the structure may comprise a semiconductor substrate, containing a source region and a drain region; a conductive gate overlying a gate dielectric layer on the semiconductor substrate; a spacer disposed adjacent to the conductive gate, the spacer having a width less than 550 angstroms; a stress film covering the source region, the drain region, the conductive gate, and the spacer.

Abstract translation: 一种提高集成电路中MOS器件的载流子迁移率的结构。 该结构包括含有源区和漏区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的共形应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 覆盖源极区域，漏极区域和导电栅极的多个应力膜。 此外，该结构可以包括含有源极区和漏极区的半导体衬底; 覆盖半导体衬底上的栅极电介质层的导电栅极; 间隔件设置成与导电栅极相邻，间隔物具有小于550埃的宽度; 覆盖源极区域，漏极区域，导电栅极和间隔物的应力膜。

公开(公告)号：US07335929B2

公开(公告)日：2008-02-26

申请号：US10967917

申请日：2004-10-18

Applicant: Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

Inventor： Chun-Chieh Lin ,  Wen-Chin Lee ,  Yee-Chia Yeo ,  Chenming Hu

IPC: H01L31/00

CPC classification number: H01L29/66636 ,  H01L29/7842 ,  H01L29/7848 ,  H01L29/802

Abstract: A transistor structure comprises a channel region overlying a substrate region. The substrate region comprises a first semiconductor material with a first lattice constant. The channel region comprises a second semiconductor material with a second lattice constant. The source and drain regions are oppositely adjacent the channel region and the top portion of the source and drain regions comprise the first semiconductor material. A gate dielectric layer overlies the channel region and a gate electrode overlies the gate dielectric layer.

Abstract translation: 晶体管结构包括覆盖衬底区域的沟道区域。 衬底区域包括具有第一晶格常数的第一半导体材料。 沟道区域包括具有第二晶格常数的第二半导体材料。 源极区和漏极区相对地邻近沟道区，并且源极和漏极区的顶部包括第一半导体材料。 栅极电介质层覆盖沟道区，栅电极覆盖在栅介质层上。

公开(公告)号：US20080035603A1

公开(公告)日：2008-02-14

申请号：US11614362

申请日：2006-12-21

Applicant: WEN-CHIN LEE ,  CHENG-HSIEN LIN

Inventor： WEN-CHIN LEE ,  CHENG-HSIEN LIN

IPC: H01B13/00 ,  B44C1/22 ,  C23F1/00

CPC classification number: C23F1/08 ,  H05K3/068 ,  H05K2203/075

Abstract: The present invention relates to an apparatus for spraying an etchant and a method for manufacturing a printed circuit board. In one exemplary embodiment the apparatus includes a manifold, a plurality of feed pipes in fluid communication with the manifold, each of the feed pipes having a plurality of spray nozzles mounted thereon, the feed pipes cooperatively constitute a spray region, and a pressure-boosting device configured for increasing a spray pressure of the spray nozzles which are located at a central area of the spray region. The apparatus can overcome “the puddle effect” on an upper surface of the printed circuit board.

Abstract translation: 本发明涉及喷涂蚀刻剂的设备和印刷电路板的制造方法。 在一个示例性实施例中，设备包括歧管，与歧管流体连通的多个进料管，每个进料管具有安装在其上的多个喷嘴，进料管协同地构成喷射区域，并且加压 该装置被配置为增加位于喷射区域的中心区域处的喷嘴的喷雾压力。 该设备可以克服印刷电路板上表面上的“水坑效应”。