公开(公告)号：US09024388B2

公开(公告)日：2015-05-05

申请号：US13919676

申请日：2013-06-17

Applicant: GlobalFoundries Inc.

Inventor： Kisik Choi ,  Ruilong Xie

IPC: H01L29/43 ,  H01L29/45 ,  H01L29/772 ,  H01L21/28 ,  H01L21/8234 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L21/823443 ,  H01L21/28008 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes forming replacement gate structures for an NMOS transistor and a PMOS transistor by forming gate insulation layers and a first metal layer for the devices from the same materials and selectively forming a metal-silicide material layer only on the first metal layer for the NMOS device but not on the PMOS device. One example of a novel integrated circuit product disclosed herein includes an NMOS device and a PMOS device wherein the gate insulation layers and the first metal layer of the gate structures of the devices are made of the same material, the gate structure of the NMOS device includes a metal silicide material positioned on the first metal layer of the NMOS device, and a second metal layer that is positioned on the metal silicide material for the NMOS device and on the first metal layer for the PMOS device.

Abstract translation: 本文公开的一种说明性方法包括通过从相同的材料形成栅极绝缘层和用于器件的第一金属层并且仅在第一金属层上选择性地形成金属硅化物材料层来形成用于NMOS晶体管和PMOS晶体管的替代栅极结构 对于NMOS器件，但不在PMOS器件上。 本文公开的新颖的集成电路产品的一个示例包括NMOS器件和PMOS器件，其中栅极绝缘层和器件的栅极结构的第一金属层由相同的材料制成，NMOS器件的栅极结构包括 位于所述NMOS器件的所述第一金属层上的金属硅化物材料，以及位于所述NMOS器件的所述金属硅化物材料上以及所述PMOS器件的所述第一金属层上的第二金属层。

公开(公告)号：US20150097246A1

公开(公告)日：2015-04-09

申请号：US14571460

申请日：2014-12-16

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Ruilong Xie ,  Pranatharthi Haran Balasubramanian

IPC: H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L27/0922 ,  H01L21/28088 ,  H01L21/823456 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/42364 ,  H01L29/4958 ,  H01L29/4966 ,  H01L29/517 ,  H01L29/66545

Abstract: An integrated circuit includes a first FET structure and a second FET structure, both of which being formed over a silicon substrate. The first FET structure includes a high-k material layer, a layer of a first workfunction material formed over the high-k material layer, a layer of a barrier material formed over the first workfunction material layer; and a layer of a gate fill material formed over the barrier material layer. The entirety of the barrier material layer and the gate fill material layer are formed above the first workfunction material layer. The second FET structure includes a layer of the high-k material, a layer of a second workfunction material formed over the high-k material layer, a low-resistance material layer formed over the second workfunction material layer and a layer of the barrier material formed over the low-resistance material layer.

Abstract translation: 集成电路包括第一FET结构和第二FET结构，它们均形成在硅衬底上。 第一FET结构包括高k材料层，形成在高k材料层上的第一功函数材料层，形成在第一功函数材料层上的阻挡材料层; 以及形成在阻挡材料层上方的栅极填充材料层。 阻挡材料层和栅极填充材料层的整体形成在第一功函数材料层的上方。 第二FET结构包括高k材料层，形成在高k材料层上的第二功函数材料层，形成在第二功函数材料层上的低电阻材料层和阻挡材料层 形成在低电阻材料层上。

公开(公告)号：US09000537B2

公开(公告)日：2015-04-07

申请号：US14333683

申请日：2014-07-17

Applicant: Globalfoundries Inc. ,  International Business Machines Corporation

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Kangguo Cheng ,  Ali Khakifirooz

IPC: H01L27/02 ,  H01L29/78 ,  H01L29/66

CPC classification number: H01L27/0207 ,  H01L29/66477 ,  H01L29/66795 ,  H01L29/78 ,  H01L29/785

Abstract: One method includes performing an etching process through a patterned mask layer to form trenches in a substrate that defines first and second fins, forming liner material adjacent the first fin to a first thickness, forming liner material adjacent the second fin to a second thickness different from the first thickness, forming insulating material in the trenches adjacent the liner materials and above the mask layer, performing a process operation to remove portions of the layer of insulating material and to expose portions of the liner materials, performing another etching process to remove portions of the liner materials and the mask layer to expose the first fin to a first height and the second fin to a second height different from the first height, performing another etching process to define a reduced-thickness layer of insulating material, and forming a gate structure around a portion of the first and second fin.

Abstract translation: 一种方法包括通过图案化的掩模层执行蚀刻工艺，以在限定第一和第二鳍片的衬底中形成沟槽，将邻近第一鳍片的衬垫材料形成第一厚度，将与第二鳍片相邻的衬垫材料形成为不同于第二厚度的第二厚度 所述第一厚度在所述沟槽中形成绝缘材料，所述沟槽邻近所述衬垫材料并且在所述掩模层上方，执行处理操作以去除所述绝缘材料层的部分并暴露所述衬垫材料的部分，执行另一蚀刻工艺以去除部分 所述衬垫材料和所述掩模层将所述第一翅片暴露于第一高度，并且所述第二鳍片具有不同于所述第一高度的第二高度，执行另一蚀刻工艺以限定绝缘材料的厚度减薄层，以及形成栅极结构 围绕第一和第二鳍的一部分。

公开(公告)号：US20150061040A1

公开(公告)日：2015-03-05

申请号：US14538401

申请日：2014-11-11

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES, INC.

Inventor： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L27/088 ,  H01L29/06

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

Abstract translation: 本发明的实施例提供一种形成半导体结构的方法。 该方法包括在衬底的顶部上形成一组器件特征; 在所述组装置特征的顶部直接形成第一介电层，并在所述基板的顶部上形成第一电介质层，从而产生从所述基板的顶表面测量的所述第一电介质层的高度分布，所述高度分布与所述基板的图案相关联 完全围绕设备特征的绝缘结构; 以及在由所述图案限定的区域中形成第二电介质层以形成所述绝缘结构。 还公开了通过该方法形成的结构。

公开(公告)号：US08962413B1

公开(公告)日：2015-02-24

申请号：US14524076

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  William J. Taylor, Jr.

IPC: H01L21/336 ,  H01L21/762 ,  H01L21/02 ,  H01L21/8234

CPC classification number: H01L29/0649 ,  H01L21/02263 ,  H01L21/76224 ,  H01L21/823431 ,  H01L21/823481 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/7851

Abstract: Disclosed herein are various methods of forming spacers on FinFETs and other semiconductor devices. In one example, the method includes forming a plurality of spaced-apart trenches in a semiconducting substrate that defines a fin, forming a first layer of insulating material in the trenches that covers a lower portion of the fin but exposes an upper portion of the fin, and forming a second layer of insulating material on the exposed upper portion of the fin. The method further comprises selectively forming a dielectric material above an upper surface of the fin and in a bottom of the trench, depositing a layer of spacer material above a gate structure of the device and above the dielectric material above the fin and in the trench, and performing an etching process on the layer of spacer material to define sidewall spacers positioned adjacent the gate structure.

Abstract translation: 这里公开了在FinFET和其它半导体器件上形成间隔物的各种方法。 在一个示例中，该方法包括在限定鳍片的半导体衬底中形成多个间隔开的沟槽，在沟槽中形成覆盖翅片下部的第一绝缘材料层，但暴露鳍片的上部 并且在所述暴露的所述翅片的上部上形成第二绝缘材料层。 所述方法还包括在所述鳍的上表面和所述沟槽的底部中选择性地形成电介质材料，在所述器件的栅极结构之上和在所述鳍上方和所述沟槽中的所述电介质材料之上沉积间隔物材料层， 以及对所述隔离层材料层进行蚀刻处理以限定邻近所述栅极结构定位的侧壁间隔物。

公开(公告)号：US20140367790A1

公开(公告)日：2014-12-18

申请号：US13919676

申请日：2013-06-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Kisik Choi ,  Ruilong Xie

IPC: H01L21/8234 ,  H01L27/092 ,  H01L21/28

CPC classification number: H01L21/823443 ,  H01L21/28008 ,  H01L21/823835 ,  H01L21/823842 ,  H01L27/092 ,  H01L29/66545

Abstract: One illustrative method disclosed herein includes forming replacement gate structures for an NMOS transistor and a PMOS transistor by forming gate insulation layers and a first metal layer for the devices from the same materials and selectively forming a metal-silicide material layer only on the first metal layer for the NMOS device but not on the PMOS device. One example of a novel integrated circuit product disclosed herein includes an NMOS device and a PMOS device wherein the gate insulation layers and the first metal layer of the gate structures of the devices are made of the same material, the gate structure of the NMOS device includes a metal silicide material positioned on the first metal layer of the NMOS device, and a second metal layer that is positioned on the metal silicide material for the NMOS device and on the first metal layer for the PMOS device.

Abstract translation: 本文公开的一种说明性方法包括通过从相同的材料形成栅极绝缘层和用于器件的第一金属层并且仅在第一金属层上选择性地形成金属硅化物材料层来形成用于NMOS晶体管和PMOS晶体管的替代栅极结构 对于NMOS器件，但不在PMOS器件上。 本文公开的新颖的集成电路产品的一个示例包括NMOS器件和PMOS器件，其中栅极绝缘层和器件的栅极结构的第一金属层由相同的材料制成，NMOS器件的栅极结构包括 位于所述NMOS器件的所述第一金属层上的金属硅化物材料，以及位于所述NMOS器件的所述金属硅化物材料上以及所述PMOS器件的所述第一金属层上的第二金属层。

公开(公告)号：US20140367788A1

公开(公告)日：2014-12-18

申请号：US13918569

申请日：2013-06-14

Applicant: GLOBALFOUNDRIES INC.

Inventor： Ruilong Xie ,  Kisik Choi

IPC: H01L21/8234 ,  H01L27/092

CPC classification number: H01L27/092 ,  H01L21/823828 ,  H01L21/823835 ,  H01L21/823842 ,  H01L29/42356 ,  H01L29/4975

Abstract: One illustrative method disclosed herein includes forming gate insulation layers and a first metal layer for NMOS and PMOS devices from the same material, selectively forming a first metal layer only for the PMOS device, and forming different shaped metal silicide regions within the NMOS and PMOS gate cavities. A novel integrated circuit product disclosed herein includes an NMOS transistor with an NMOS gate insulation layer, an NMOS metal silicide having a generally rectangular cross-sectional configuration and an NMOS metal layer positioned on the NMOS metal silicide region. The product also includes a PMOS transistor with the same gate insulation material, a first PMOS metal and a PMOS metal silicide region, wherein the NMOS and PMOS metal silicide regions are comprised of the same metal silicide.

Abstract translation: 本文公开的一种说明性方法包括从相同材料形成用于NMOS和PMOS器件的栅极绝缘层和第一金属层，仅选择性地形成用于PMOS器件的第一金属层，以及在NMOS和PMOS栅极内形成不同形状的金属硅化物区域 空腔 本文公开的新型集成电路产品包括具有NMOS栅极绝缘层的NMOS晶体管，具有大致矩形横截面构造的NMOS金属硅化物和位于NMOS金属硅化物区域上的NMOS金属层。 该产品还包括具有相同栅极绝缘材料的PMOS晶体管，第一PMOS金属和PMOS金属硅化物区域，其中NMOS和PMOS金属硅化物区域由相同的金属硅化物组成。

公开(公告)号：US20140346599A1

公开(公告)日：2014-11-27

申请号：US13902369

申请日：2013-05-24

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Songkram Srivathanakul

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/7851

Abstract: FinFET semiconductor devices with local isolation features and methods for fabricating such devices are provided. In one embodiment, a method for fabricating a semiconductor device includes providing a semiconductor substrate comprising a plurality of fin structures formed thereon, wherein each of the plurality of fin structures has sidewalls, forming spacers about the sidewalls of the plurality of fin structures, and forming a silicon-containing layer over the semiconductor substrate and in between the plurality of fin structures. The method further includes removing at least a first portion of the silicon-containing layer to form a plurality of void regions while leaving at least a second portion thereof in place and depositing an isolation material in the plurality of void regions.

Abstract translation: 提供具有局部隔离特征的FinFET半导体器件和用于制造这种器件的方法。 在一个实施例中，制造半导体器件的方法包括提供包括形成在其上的多个翅片结构的半导体衬底，其中，所述多个翅片结构中的每一个具有侧壁，围绕所述多个鳍结构的侧壁形成间隔件，以及形成 位于所述半导体衬底上并位于所述多个翅片结构之间的含硅层。 该方法还包括移除含硅层的至少第一部分以形成多个空隙区域，同时至少留下第二部分，并在多个空隙区域中沉积隔离材料。

公开(公告)号：US20140264479A1

公开(公告)日：2014-09-18

申请号：US13797001

申请日：2013-03-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  Ali Khakifirooz ,  Kangguo Cheng

IPC: H01L29/40 ,  H01L29/417

CPC classification number: H01L29/401 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76897 ,  H01L29/41775 ,  H01L29/41783 ,  H01L29/66545 ,  H01L29/66575 ,  H01L29/66636

Abstract: One method includes forming a sidewall spacer adjacent a gate structure, forming a first liner layer on the sidewall spacer, forming a second liner layer on the first liner layer, forming a first layer of insulating material above the substrate and adjacent the second liner layer, selectively removing at least portions of the second liner layer relative to the first liner layer, forming a second layer of insulating material above the first layer of insulating material, performing at least one second etching process to remove at least portions of the first and second layers of insulating material and at least portions of the first liner layer so as to thereby expose an outer surface of the sidewall spacer, and forming a conductive contact that contacts the exposed outer surface of the sidewall spacer and a source/drain region of the transistor.

Abstract translation: 一种方法包括在栅极结构附近形成侧壁间隔物，在侧壁间隔物上形成第一衬里层，在第一衬里层上形成第二衬里层，在衬底上方形成第一绝缘材料层并邻近第二衬层， 选择性地去除所述第二衬层的至少部分相对于所述第一衬层，在所述第一绝缘材料层之上形成第二绝缘材料层，执行至少一个第二蚀刻工艺以移除所述第一层和所述第二层的至少一部分 的绝缘材料和第一衬里层的至少部分，从而暴露侧壁间隔件的外表面，并且形成接触暴露的侧壁间隔物的外表面和晶体管的源极/漏极区域的导电接触。

公开(公告)号：US20140252424A1

公开(公告)日：2014-09-11

申请号：US13785403

申请日：2013-03-05

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xiuyu Cai ,  Ruilong Xie ,  John A. Iacoponi

IPC: H01L21/768 ,  H01L23/48 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L21/76831 ,  H01L21/76897 ,  H01L21/823821 ,  H01L21/82385 ,  H01L21/823864 ,  H01L29/785 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One method discloses performing an etching process to form a contact opening in a layer of insulating material above at least a portion of a source/drain, region wherein, after the completion of the etching process, a portion of a gate structure of the transistor is exposed, selectively forming an oxidizable material on the exposed gate structure, converting at least a portion of the oxidizable material to an oxide material, and forming a conductive contact in the contact opening that is conductively coupled to the source/drain region. A novel transistor device disclosed herein includes an oxide material positioned between a conductive contact and a gate structure of the transistor, wherein the oxide material contacts the conductive contact and contacts a portion, but not all, of the exterior surface of the gate structure.

Abstract translation: 一种方法公开了进行蚀刻工艺以在源极/漏极区域的至少一部分上方的绝缘材料层中形成接触开口，其中在蚀刻工艺完成之后，晶体管的栅极结构的一部分是 暴露的，在暴露的栅极结构上选择性地形成可氧化材料，将可氧化材料的至少一部分转化为氧化物材料，以及在导电耦合到源/漏区的接触开口中形成导电接触。 本文公开的新型晶体管器件包括位于晶体管的导电接触和栅极结构之间的氧化物材料，其中氧化物材料接触导电接触并接触栅极结构的外表面的一部分但不全部接触。