公开(公告)号：US20190164836A1

公开(公告)日：2019-05-30

申请号：US15859327

申请日：2017-12-29

Applicant: Intel Corporation

Inventor： Tahir GHANI ,  Byron HO ,  Curtis W. WARD ,  Michael L. HATTENDORF ,  Christopher P. AUTH

IPC: H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/78 ,  H01L27/088

Abstract: Embodiments of the disclosure are in the field of advanced integrated circuit structure fabrication and, in particular, 10 nanometer node and smaller integrated circuit structure fabrication and the resulting structures. In an example, an integrated circuit structure includes a fin. A first isolation structure separates a first end of a first portion of the fin from a first end of a second portion of the fin, the first end of the first portion of the fin having a depth. A gate structure is over the top of and laterally adjacent to the sidewalls of a region of the first portion of the fin. A second isolation structure is over a second end of a first portion of the fin, the second end of the first portion of the fin having a depth different than the depth of the first end of the first portion of the fin.

公开(公告)号：US20190148512A1

公开(公告)日：2019-05-16

申请号：US16099418

申请日：2016-07-02

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Sean T. MA ,  Chandra S. MOHAPATRA ,  Sanaz K. GARDNER ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/78 ,  H01L29/417 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02 ,  H01L21/768

Abstract: An apparatus including a transistor device including a body including a channel region between a source region and a drain region; and a gate stack on the body in the channel region, wherein at least one of the source region and the drain region of the body include a contact surface between opposing sidewalls and the contact surface includes a profile such that a height dimension of the contact surface is greater at the sidewalls than at a point between the sidewalls. A method including forming a transistor device body on a circuit substrate, the transistor device body dimension defining a channel region between a source region and a drain region; forming a groove in the body in at least one of the source region and the drain region; and forming a gate stack on the body in the channel region.

公开(公告)号：US20190140054A1

公开(公告)日：2019-05-09

申请号：US16095287

申请日：2016-06-30

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Matthew V. METZ ,  Willy RACHMADY ,  Anand S. MURTHY ,  Chandra S. MOHAPATRA ,  Tahir GHANI ,  Sean T. MA ,  Jack T. KAVALIEROS

IPC: H01L29/10 ,  H01L29/78 ,  H01L29/66

Abstract: An apparatus is described. The apparatus includes a FINFET device having a channel. The channel is composed of a first semiconductor material that is epitaxially grown on a subfin structure beneath the channel. The subfin structure is composed of a second semiconductor material that is different than the first semiconductor material. The subfm structure is epitaxially grown on a substrate composed of a third semiconductor material that is different than the first and second semiconductor materials. The subfin structure has a doped region to substantially impede leakage currents between the channel and the substrate.

公开(公告)号：US20190051725A1

公开(公告)日：2019-02-14

申请号：US16153456

申请日：2018-10-05

Applicant: Intel Corporation

Inventor： Seiyon KIM ,  Kelin J. KUHN ,  Tahir GHANI ,  Anand S. MURTHY ,  Mark ARMSTRONG ,  Rafael RIOS ,  Abhijit Jayant PETHE ,  Willy RACHMADY

IPC: H01L29/06 ,  H01L29/423

Abstract: A nanowire device having a plurality of internal spacers and a method for forming said internal spacers are disclosed. In an embodiment, a semiconductor device comprises a nanowire stack disposed above a substrate, the nanowire stack having a plurality of vertically-stacked nanowires, a gate structure wrapped around each of the plurality of nanowires, defining a channel region of the device, the gate structure having gate sidewalls, a pair of source/drain regions on opposite sides of the channel region; and an internal spacer on a portion of the gate sidewall between two adjacent nanowires, internal to the nanowire stack. In an embodiment, the internal spacers are formed by depositing spacer material in dimples etched adjacent to the channel region. In an embodiment, the dimples are etched through the channel region. In another embodiment, the dimples are etched through the source/drain region.

公开(公告)号：US20180315757A1

公开(公告)日：2018-11-01

申请号：US15771080

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Chandra S. MOHAPATRA ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI

IPC: H01L27/092 ,  H01L21/8258 ,  H01L21/8238 ,  H01L27/088

Abstract: Embodiments of the invention include a semiconductor structure and a method of making such a structure. In one embodiment, the semiconductor structure comprises a first fin and a second fin formed over a substrate. The first fin may comprise a first semiconductor material and the second fin may comprise a second semiconductor material. In an embodiment, a first cage structure is formed adjacent to the first fin, and a second cage structure is formed adjacent to the second fin. Additionally, embodiments may include a first gate electrode formed over the first fin, where the first cage structure directly contacts the first gate electrode, and a second gate electrode formed over the second fin, where the second cage structure directly contacts the second gate electrode.

公开(公告)号：US20180158957A1

公开(公告)日：2018-06-07

申请号：US15575111

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Chandra S. MOHAPATRA ,  Jack T. KAVALIEROS ,  Anand S. MURTHY ,  Tahir GHANI ,  Nadia M. RAHHAL-ORABI ,  Sanaz K. GARDNER

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66

CPC classification number: H01L29/78609 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66742 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: Crystalline heterostructures including an elevated fin structure extending from a sub-fin structure over a substrate. Devices, such as III-V transistors, may be formed on the raised fin structures while silicon-based devices (e.g., transistors) may be formed in other regions of the silicon substrate. A sub-fin isolation material localized to a transistor channel region of the fin structure may reduce source-to-drain leakage through the sub-fin, improving electrical isolation between source and drain ends of the fin structure. Subsequent to heteroepitaxially forming the fin structure, a portion of the sub-fin may be laterally etched to undercut the fin. The undercut is backfilled with sub-fin isolation material. A gate stack is formed over the fin. Formation of the sub-fin isolation material may be integrated into a self-aligned gate stack replacement process.

公开(公告)号：US20170323963A1

公开(公告)日：2017-11-09

申请号：US15528802

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia RAHHAL-ORABI ,  Nancy M. ZELICK ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/66818

Abstract: An embodiment includes a device comprising: a fin structure including an upper portion and a lower portion, the upper portion having a bottom surface directly contacting an upper surface of the lower portion; wherein (a) the lower portion is included in a trench having an aspect ratio (depth to width) of at least 2:1; (b) the bottom surface has a bottom maximum width and the upper surface has an upper maximum width that is greater the bottom maximum width; (c) the bottom surface covers a middle portion of the upper surface but does not cover lateral portions of the upper surface; and (d) the upper portion includes an upper III-V material and the lower portion includes a lower III-V material different from the upper III-V material. Other embodiments are described herein.

公开(公告)号：US20170162676A1

公开(公告)日：2017-06-08

申请号：US15434981

申请日：2017-02-16

Applicant: Intel Corporation

Inventor： Annalisa CAPPELLANI ,  Stephen M. CEA ,  Tahir GHANI ,  Harry GOMEZ ,  Jack T. KAVALIEROS ,  Patrick H. KEYS ,  Seiyon KIM ,  Kelin J. KUHN ,  Aaron D. LILAK ,  Rafael RIOS ,  Mayank SAHNI

IPC: H01L29/66 ,  H01L21/762 ,  H01L29/423 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66818 ,  B82Y10/00 ,  H01L21/762 ,  H01L21/76216 ,  H01L27/1203 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785

Abstract: Semiconductor devices with isolated body portions are described. For example, a semiconductor structure includes a semiconductor body disposed above a semiconductor substrate. The semiconductor body includes a channel region and a pair of source and drain regions on either side of the channel region. An isolation pedestal is disposed between the semiconductor body and the semiconductor substrate. A gate electrode stack at least partially surrounds a portion of the channel region of the semiconductor body.

公开(公告)号：US20250142870A1

公开(公告)日：2025-05-01

申请号：US19004029

申请日：2024-12-27

Applicant: Intel Corporation

Inventor： Cory BOMBERGER ,  Anand S. MURTHY ,  Tahir GHANI ,  Anupama BOWONDER

IPC: H10D30/62 ,  H10D30/01 ,  H10D62/822

Abstract: Fin smoothing, and integrated circuit structures resulting therefrom, are described. For example, an integrated circuit structure includes a semiconductor fin having a protruding fin portion above an isolation structure, the protruding fin portion having substantially vertical sidewalls. The semiconductor fin further includes a sub-fin portion within an opening in the isolation structure, the sub-fin portion having a different semiconductor material than the protruding fin portion. The sub-fin portion has a width greater than or less than a width of the protruding portion where the sub-fin portion meets the protruding portion. A gate stack is over and conformal with the protruding fin portion of the semiconductor fin. A first source or drain region at a first side of the gate stack, and a second source or drain region at a second side of the gate stack opposite the first side of the gate stack.

公开(公告)号：US20250113550A1

公开(公告)日：2025-04-03

申请号：US18980999

申请日：2024-12-13

Applicant: Intel Corporation

Inventor： Glenn GLASS ,  Anand MURTHY ,  Biswajeet GUHA ,  Tahir GHANI ,  Susmita GHOSE ,  Zachary GEIGER

IPC: H01L29/786 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423

Abstract: Gate-all-around integrated circuit structures having nanowires with tight vertical spacing, and methods of fabricating gate-all-around integrated circuit structures having nanowires with tight vertical spacing, are described. For example, an integrated circuit structure includes a vertical arrangement of horizontal silicon nanowires. A vertical spacing between vertically adjacent silicon nanowires is less than 6 nanometers. A gate stack is around the vertical arrangement of horizontal silicon nanowires. A first source or drain structure is at a first end of the vertical arrangement of horizontal silicon nanowires, and a second epitaxial source or drain structure is at a second end of the vertical arrangement of horizontal silicon nanowires.