公开(公告)号：US20170317187A1

公开(公告)日：2017-11-02

申请号：US15528793

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia RAHHAL-ORABI ,  Nancy M. ZELICK ,  Marc C. FRENCH ,  Tahir GHANI

IPC: H01L29/66 ,  H01L29/786 ,  H01L29/423 ,  H01L29/06 ,  H01L27/088 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L29/66742 ,  B82Y10/00 ,  H01L21/02392 ,  H01L21/02546 ,  H01L21/02603 ,  H01L21/823412 ,  H01L27/088 ,  H01L29/0673 ,  H01L29/20 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66522 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/785 ,  H01L29/78681 ,  H01L29/78696

Abstract: An embodiment includes a device comprising: first and second fins adjacent one another and each including channel and subfin layers, the channel layers having bottom surfaces directly contacting upper surfaces of the subfin layers; wherein (a) the bottom surfaces are generally coplanar with one another and are generally flat; (b) the upper surfaces are generally coplanar with one another and are generally flat; and (c) the channel layers include an upper material and the subfin layers include a lower III-V material different from the upper III-V material. Other embodiments are described herein.

公开(公告)号：US20170323963A1

公开(公告)日：2017-11-09

申请号：US15528802

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia RAHHAL-ORABI ,  Nancy M. ZELICK ,  Tahir GHANI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/205 ,  H01L29/66

CPC classification number: H01L29/785 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/66818

Abstract: An embodiment includes a device comprising: a fin structure including an upper portion and a lower portion, the upper portion having a bottom surface directly contacting an upper surface of the lower portion; wherein (a) the lower portion is included in a trench having an aspect ratio (depth to width) of at least 2:1; (b) the bottom surface has a bottom maximum width and the upper surface has an upper maximum width that is greater the bottom maximum width; (c) the bottom surface covers a middle portion of the upper surface but does not cover lateral portions of the upper surface; and (d) the upper portion includes an upper III-V material and the lower portion includes a lower III-V material different from the upper III-V material. Other embodiments are described herein.

公开(公告)号：US20170186598A1

公开(公告)日：2017-06-29

申请号：US15458897

申请日：2017-03-14

Applicant: Intel Corporation

Inventor： Niti Goel ,  Robert S. CHAU ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Nancy M. ZELICK ,  Gilbert DEWEY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Ravi PILLARISETTY ,  Sansaptak DASGUPTA

IPC: H01L21/02 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/20 ,  H01L27/092 ,  H01L29/06

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

公开(公告)号：US20170365681A1

公开(公告)日：2017-12-21

申请号：US15679077

申请日：2017-08-16

Applicant: Intel Corporation

Inventor： Gilbert DEWEY ,  Niloy MUKHERJEE ,  Matthew METZ ,  Jack T. KAVALIEROS ,  Nancy M. ZELICK ,  Robert S. CHAU

IPC: H01L29/51 ,  H01L21/285 ,  H01L21/324 ,  H01L21/768 ,  H01L29/66 ,  H01L23/532 ,  H01L29/49 ,  H01L23/485 ,  H01L29/78 ,  H01L45/00 ,  H01L33/40 ,  H01L33/00 ,  H01L31/0224 ,  H01L29/45 ,  H01L21/04 ,  H01L51/10 ,  H01L51/44 ,  H01L51/52 ,  H01B1/12

Abstract: An interlayer is used to reduce Fermi-level pinning phenomena in a semiconductive device with a semiconductive substrate. The interlayer may be a rare-earth oxide. The interlayer may be an ionic semiconductor. A metallic barrier film may be disposed between the interlayer and a metallic coupling. The interlayer may be a thermal-process combination of the metallic barrier film and the semiconductive substrate. A process of forming the interlayer may include grading the interlayer. A computing system includes the interlayer.

公开(公告)号：US20170263706A1

公开(公告)日：2017-09-14

申请号：US15529481

申请日：2014-12-24

Applicant: INTEL CORPORATION

Inventor： Sanaz K. GARDNER ,  Willy RACHMADY ,  Matthew V. METZ ,  Gilbert DEWEY ,  Jack T. KAVALIEROS ,  Chandra S. MOHAPATRA ,  Anand S. MURTHY ,  Nadia M. RAHHAL-ORABI ,  Nancy M. ZELICK ,  Tahir GHANI

IPC: H01L29/06 ,  H01L29/04 ,  H01L29/205 ,  H01L29/78 ,  H01L29/66 ,  H01L21/762

CPC classification number: H01L29/0673 ,  H01L21/76224 ,  H01L29/045 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/205 ,  H01L29/267 ,  H01L29/42392 ,  H01L29/66522 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785 ,  H01L29/78696

Abstract: Embodiments of the invention include nanowire and nanoribbon transistors and methods of forming such transistors. According to an embodiment, a method for forming a microelectronic device may include forming a multi-layer stack within a trench formed in a shallow trench isolation (STI) layer. The multi-layer stack may comprise at least a channel layer, a release layer formed below the channel layer, and a buffer layer formed below the channel layer. The STI layer may be recessed so that a top surface of the STI layer is below a top surface of the release layer. The exposed release layer from below the channel layer by selectively etching away the release layer relative to the channel layer.

公开(公告)号：US20160211263A1

公开(公告)日：2016-07-21

申请号：US14915185

申请日：2013-09-27

Applicant: INTEL CORPORATION

Inventor： Niti GOEL ,  Robert S. CHAU ,  Jack T. KAVALIEROS ,  Benjamin CHU-KUNG ,  Matthew V. METZ ,  Niloy MUKHERJEE ,  Nancy M. ZELICK ,  Gilbert DEWEY ,  Willy RACHMADY ,  Marko RADOSAVLJEVIC ,  Van H. LE ,  Ravi PILLARISETTY ,  Sansaptak DASGUPTA

IPC: H01L27/092 ,  H01L29/06 ,  H01L29/205 ,  H01L21/8238 ,  H01L21/8252 ,  H01L29/165 ,  H01L29/66 ,  H01L21/02

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02461 ,  H01L21/02463 ,  H01L21/02502 ,  H01L21/02532 ,  H01L21/02543 ,  H01L21/02546 ,  H01L21/02598 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823878 ,  H01L21/8252 ,  H01L27/0922 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/1054 ,  H01L29/16 ,  H01L29/165 ,  H01L29/20 ,  H01L29/205 ,  H01L29/66795 ,  H01L29/785

Abstract: A single fin or a pair of co-integrated n- and p-type single crystal electronic device fins are epitaxially grown from a substrate surface at a bottom of one or a pair of trenches formed between shallow trench isolation (STI) regions. The fin or fins are patterned and the STI regions are etched to form a height of the fin or fins extending above etched top surfaces of the STI regions. The fin heights may be at least 1.5 times their width. The exposed sidewall surfaces and a top surface of each fin is epitaxially clad with one or more conformal epitaxial materials to form device layers on the fin. Prior to growing the fins, a blanket buffer epitaxial material may be grown from the substrate surface; and the fins grown in STI trenches formed above the blanket layer. Such formation of fins reduces defects from material interface lattice mismatches.

Abstract translation: 从形成在浅沟槽隔离（STI）区域之间的一个或一对沟槽的底部的衬底表面外延生长单个鳍或一对共同组合的n型和p型单晶电子器件鳍。 翅片或翅片被图案化并且STI区域被蚀刻以形成在STI区域的蚀刻顶表面之上延伸的翅片或翅片的高度。 翅片高度可以是其宽度的至少1.5倍。 暴露的侧壁表面和每个翅片的顶表面用一个或多个共形外延材料外延包层以在翅片上形成器件层。 在生长翅片之前，可以从衬底表面生长毯式缓冲外延材料; 并且生长在STI沟槽中的翅片形成在覆盖层上方。 翅片的这种形成减少了材料界面晶格失配的缺陷。