公开(公告)号：US20180336951A1

公开(公告)日：2018-11-22

申请号：US16048506

申请日：2018-07-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Akira Goda ,  Mason A. Jones

IPC: G11C16/10 ,  G11C16/04 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3427

Abstract: A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected memory string of the memory device, discharging the boosted channels of the memory cells in the selected memory string, and programming a selected memory cell in the selected memory string after discharging the boosted channels in the selected memory string.

公开(公告)号：US20180322933A1

公开(公告)日：2018-11-08

申请号：US16035857

申请日：2018-07-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Goda ,  Yijie Zhao ,  Krishna Parat

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/10

Abstract: Memory devices including a controller configured to cause the memory device to apply a positive first voltage level to a first data line selectively connected to a first string of series-connected memory cells while applying a second voltage level, higher than the first voltage level, to a second data line selectively connected to a second string of series-connected memory cells; while applying the first voltage level to the first data line and applying the second voltage level to the second data line, applying a third voltage level to a particular access line coupled to a memory cell of a first string of series-connected memory cells selected for programming, wherein a differential between the third voltage level and the first voltage level is configured to increase a threshold voltage of the memory cell selected for programming, as well as other apparatus containing similar memory devices.

公开(公告)号：US10090310B2

公开(公告)日：2018-10-02

申请号：US14456479

申请日：2014-08-11

Applicant: Micron Technology, Inc.

Inventor： Akira Goda

IPC: G11C16/04 ,  H01L27/115 ,  H01L27/11556 ,  H01L27/11582 ,  H01L29/788 ,  H01L29/792 ,  G11C7/00 ,  H01L29/78 ,  G11C16/10 ,  G11C16/26 ,  H01L27/11519 ,  H01L27/11524 ,  H01L27/11565 ,  H01L27/1157

Abstract: Memory devices and methods of operating memory devices are shown. Configurations described include a memory cell string having an elongated n type body region and having select gates with p type bodies. Configurations and methods shown can provide a reliable bias to a body region for memory operations such as erasing.

公开(公告)号：US09953718B2

公开(公告)日：2018-04-24

申请号：US15437584

申请日：2017-02-21

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Carmine Miccoli ,  Christian Caillat ,  Akira Goda

IPC: G11C11/34 ,  G11C16/04 ,  G11C16/34 ,  G11C11/56

CPC classification number: G11C16/3427 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3418 ,  G11C16/3459 ,  G11C2211/5622

Abstract: First memory cells are programmed to an intermediate level from a lowest level, corresponding to a lowest data state, where the first memory cells are to be programmed from the intermediate level to levels other than the lowest level. The first memory cells are not read or verified at the intermediate level. Different first memory cells of the first memory cells that are programmed to the intermediate level are respectively programmed to different levels of the levels other than the lowest level from the intermediate level. A second memory cell is programmed to a lower level than the different levels of the levels other than the lowest level from the lowest level while the different first memory cells are respectively programmed to the different levels of the levels other than the lowest level from the intermediate level.

公开(公告)号：US09779817B2

公开(公告)日：2017-10-03

申请号：US14740685

申请日：2015-06-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Violante Moschiano ,  Akira Goda ,  Mason A. Jones

IPC: G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/3427

Abstract: A method for programming a non-volatile memory device includes concurrently boosting channels of memory cells in a selected memory string and an unselected memory string of the memory device, discharging the boosted channels of the memory cells in the selected memory string, and programming a selected memory cell in the selected memory string after discharging the boosted channels in the selected memory string.

公开(公告)号：US09779816B2

公开(公告)日：2017-10-03

申请号：US15166029

申请日：2016-05-26

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582 ,  G11C16/26 ,  G11C16/34 ,  G11C16/12 ,  G11C16/14 ,  G11C16/06 ,  G11C16/10

CPC classification number: G11C16/0483 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

公开(公告)号：US09754671B2

公开(公告)日：2017-09-05

申请号：US15248130

申请日：2016-08-26

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Yijie Zhao ,  Akira Goda

IPC: G11C16/00 ,  G11C16/12 ,  G11C16/04 ,  G11C16/10 ,  G11C16/34

CPC classification number: G11C16/12 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3427 ,  G11C16/3454

Abstract: A method of programming a memory includes boosting a channel voltage while a first portion of a plurality of increasing programming pulses is applied to a selected access line, and when a criteria is met, reducing the channel voltage to a reduced voltage level and subsequently boosting the channel voltage, starting from the reduced voltage level, while a second portion of the plurality of increasing programming pulses is applied to the selected access line. Differences between the channel voltage boosted while the first portion of the plurality of increasing programming pulses is applied and voltages of the first portion of the plurality of increasing programming pulses are substantially the same as differences between the channel voltage boosted while the second portion of the plurality of increasing programming pulses is applied and voltages of the second portion of the plurality of increasing programming pulses.

公开(公告)号：US20160343438A1

公开(公告)日：2016-11-24

申请号：US15166029

申请日：2016-05-26

Applicant: Micron Technology, Inc.

Inventor： Akira Goda ,  Shafqat Ahmed ,  Khaled Hasnat ,  Krishna K. Parat

IPC: G11C16/04 ,  H01L27/115 ,  G11C16/06

CPC classification number: G11C16/0483 ,  G11C16/0408 ,  G11C16/06 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/11519 ,  H01L27/11556 ,  H01L27/11565 ,  H01L27/11582

Abstract: Apparatus and methods are disclosed, such as an apparatus that includes a string of charge storage devices associated with a pillar (e.g., of semiconductor material), a source gate device, and a source select device coupled between the source gate device and the string. Additional apparatus and methods are described.

公开(公告)号：US09437304B2

公开(公告)日：2016-09-06

申请号：US14857475

申请日：2015-09-17

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Akira Goda ,  Haitao Liu ,  Krishna Parat

IPC: G11C16/04 ,  G11C16/10 ,  H01L27/115

CPC classification number: G11C16/10 ,  G11C16/0483 ,  H01L27/11556 ,  H01L27/11582

Abstract: An embodiment of a method includes decreasing a difference of a voltage applied to a first select gate minus a voltage applied to a source while the first select gate is off, decreasing a difference of a voltage applied to a second select gate minus a voltage applied to a data line while the second select gate is off, and increasing a voltage of a signal applied to a selected access line that is coupled to an untargeted memory cell in a string of memory cells coupled to the first and second select gates to a program voltage after or substantially concurrently with decreasing the difference of the voltage applied to the first select gate minus the voltage applied to the source and with decreasing the difference of the voltage applied to the second select gate minus the voltage applied to the data line.

公开(公告)号：US09362300B2

公开(公告)日：2016-06-07

申请号：US14509621

申请日：2014-10-08

Applicant: Micron Technology, Inc.

Inventor： Zhenyu Lu ,  Roger W. Lindsay ,  Akira Goda ,  John Hopkins

IPC: G11C16/04 ,  H01L27/115 ,  G11C16/14 ,  G11C16/34 ,  H01L29/788 ,  H01L29/792 ,  H01L21/02 ,  G11C16/26

CPC classification number: H01L27/11582 ,  G11C16/04 ,  G11C16/0475 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3445 ,  H01L21/02178 ,  H01L27/11524 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11573

Abstract: Some embodiments include apparatuses and methods having multiple decks of memory cells and associated control gates. A method includes forming a first deck having alternating conductor materials and dielectric materials and a hole containing materials extending through the conductor materials and the dielectric materials. The methods can also include forming a sacrificial material in an enlarged portion of the hole and forming a second deck of memory cells over the first deck. Additional apparatuses and methods are described.

Abstract translation: 一些实施例包括具有多层存储器单元和相关控制门的装置和方法。 一种方法包括形成具有交替的导体材料和电介质材料的第一甲板和包含延伸穿过导体材料和电介质材料的材料的孔。 所述方法还可以包括在所述孔的扩大部分中形成牺牲材料并在所述第一甲板上形成第二层记忆单元。 描述附加的装置和方法。