公开(公告)号：US6030870A

公开(公告)日：2000-02-29

申请号：US960561

申请日：1997-10-29

Applicant: Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

Inventor： Angelo Magri' ,  Ferruccio Frisina ,  Giuseppe Ferla

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/78

CPC classification number: H01L29/66712 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/7802 ,  H01L29/0847

Abstract: A MOS technology power device comprises a semiconductor material layer of a first conductivity type, a plurality of elementary functional units, a first insulating material layer placed above the semiconductor material layer and a conductive material layer placed above the first insulating material layer. Each elementary functional unit includes an elongated body region of a second conductivity type formed in the semiconductor material layer. Each elementary functional unit further includes a first elongated window in the conductive material layer extending above the elongated body region. Each elongated body region includes a source region doped with dopants of the first conductivity type, intercalated with a portion of the elongated body region wherein no dopant of the first conductivity type are provided. The MOS technology power device further includes a second insulating material layer disposed above the conductive material layer and disposed along elongated edges of the first elongated window. The second insulating material layer includes a second elongated window extending above each elongated body region. The second insulating material layer seals the edges of the conductive material layer from a source metal layer disposed over the second insulating material layer. The source metal layer contacts each body region and each source region through each second elongated window along the length of the elongated body region.

公开(公告)号：US6022778A

公开(公告)日：2000-02-08

申请号：US612722

申请日：1996-03-08

Applicant: Claudio Contiero ,  Paola Galbiati ,  Michele Palmieri

Inventor： Claudio Contiero ,  Paola Galbiati ,  Michele Palmieri

IPC: H01L21/265 ,  H01L21/336 ,  H01L21/8222 ,  H01L21/8234 ,  H01L21/8247 ,  H01L21/8248 ,  H01L21/8249 ,  H01L27/06 ,  H01L27/088 ,  H01L27/115 ,  H01L29/08 ,  H01L29/78 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L29/66659 ,  H01L21/823456 ,  H01L27/11526 ,  H01L27/11546 ,  H01L29/66674 ,  H01L29/7816 ,  H01L29/0847

Abstract: A process for the manufacturing of an integrated circuit having DMOS-technology power devices and non-volatile memory cells provides for forming respective laterally displaced isolated semiconductor regions, electrically insulated from each other and from a common semiconductor substrate, inside which the devices will be formed; forming conductive gate regions for the DMOS-technology power devices and for the memory cells over the respective isolated semiconductor regions. Inside the isolated semiconductor regions for the DMOS-technology power devices, channel regions extending under the insulated gate regions are formed. The channel regions are formed by an implantation of a dopant along directions tilted of a prescribed angle with respect to a direction orthogonal to a top surface of the integrated circuit, in a dose and with an energy such that the channel regions are formed directly after the implantation of the dopant without performing a thermal diffusion at a high temperature of the dopant.

Abstract translation: 用于制造具有DMOS技术功率器件和非易失性存储器单元的集成电路的工艺提供了形成相互电绝缘的相互横向偏移的隔离半导体区域以及将形成器件的共用半导体衬底 ; 形成用于DMOS技术功率器件和各个隔离半导体区域上的存储器单元的导电栅极区域。 在用于DMOS技术功率器件的隔离半导体区域内部，形成在绝缘栅极区域下延伸的沟道区域。 通过以剂量和能量使掺杂剂沿相对于与集成电路的顶表面正交的方向倾斜规定角度的方向注入形成沟道区，使得沟道区直接形成在 注入掺杂剂而不在掺杂剂的高温下进行热扩散。

公开(公告)号：US6005411A

公开(公告)日：1999-12-21

申请号：US777296

申请日：1996-12-27

Applicant: Vincenzo Daniele

Inventor： Vincenzo Daniele

IPC: H03K19/173 ,  H03K19/177 ,  H03K19/094

CPC classification number: H03K19/17708 ,  H03K19/1736

Abstract: The present invention is a monolithically integrated programmable device having elementary modules connected electrically by means of memory cells of the flash type, which cells allow the signal paths between signal lines of the elementary modules to be programmed and re-programmed. Preferably, the flash memory cells are Fowler-Nordheim Effect cells.

Abstract translation: 本发明是具有通过闪存类型的存储器单元电连接的基本模块的单片集成可编程器件，这些单元允许对基本模块的信号线之间的信号路径进行编程和重新编程。 优选地，闪存单元是Fowler-Nordheim Effect细胞。

公开(公告)号：US5999445A

公开(公告)日：1999-12-07

申请号：US916874

申请日：1997-08-22

Applicant: Paolo Rolandi ,  Cristiano Calligaro ,  Alessandro Manstretta ,  Guido Torelli

Inventor： Paolo Rolandi ,  Cristiano Calligaro ,  Alessandro Manstretta ,  Guido Torelli

IPC: G11C16/02 ,  G11C11/56 ,  G11C11/34

CPC classification number: G11C11/5621 ,  G11C11/5628 ,  G11C16/102 ,  G11C2211/5621

Abstract: In a storage device of the multi-level type, comprising a plurality of memory cells addressable through an address input each cell being adapted for storing more than one binary information element in a MOS transistor which has a control gate, and a floating gate for storing electrons to modify the threshold voltage of the transistor, and comprising a circuit enabling a Direct Memory Access (DMA) mode for directly accessing the memory cells from outside the device, the memory cells are programmed in the direct memory access mode by controlling, from outside the device, the amount of charge stored into the floating gate of each transistor.

Abstract translation: 在多级类型的存储装置中，包括可通过地址输入寻址的多个存储器单元，每个单元适于在具有控制栅极的MOS晶体管中存储多于一个二进制信息元素，以及用于存储的浮动栅极 电子来修改晶体管的阈值电压，并且包括能够直接存储器访问（DMA）模式的电路，用于从设备外部直接访问存储器单元，通过从外部控制来将存储器单元编程为直接存储器访问模式 该器件，每个晶体管的浮置栅极存储的电荷量。

公开(公告)号：US5994960A

公开(公告)日：1999-11-30

申请号：US948562

申请日：1997-10-10

Applicant: Andrea Baschirotto ,  Angelo Nagari ,  Rinaldo Castello

Inventor： Andrea Baschirotto ,  Angelo Nagari ,  Rinaldo Castello

IPC: H03F1/08 ,  H03F3/72 ,  H03F3/45 ,  H03F1/14

CPC classification number: H03F3/72 ,  H03F1/086 ,  H03F2200/513

Abstract: In a switched operational amplifier including a differential input stage and at least a second output stage, the compensation capacitor commonly required to couple the output node of the second stage with the respective output node of the input differential stage of the amplifier is associated with a switching circuit. The switching circuit is controlled by the same control phase that enables/disables the amplifier for interrupting the connection between the compensation capacitor (CC) and the output node of the differential input stage during a phase in which the amplifier is disabled for reducing the switch-on time. Notably the differential input stage of the operational amplifier remains always active and only the second output stage is switched on and off.

Abstract translation: 在包括差分输入级和至少第二输出级的开关运算放大器中，将第二级的输出节点与放大器的输入差分级的相应输出节点耦合起来的补偿电容器与切换 电路。 开关电路由相同的控制相位控制，使得放大器能够在禁止放大器以减少开关电流的相位期间中断补偿电容器（CC）和差分输入级的输出节点之间的连接， 准时。 值得注意的是，运算放大器的差分输入级保持始终有效，只有第二个输出级接通和关断。

公开(公告)号：US5986921A

公开(公告)日：1999-11-16

申请号：US883822

申请日：1997-06-27

Applicant: Cristiano Calligaro ,  Nicola Telecco ,  Guido Torelli

Inventor： Cristiano Calligaro ,  Nicola Telecco ,  Guido Torelli

IPC: G11C16/06 ,  G11C11/56 ,  G11C16/02 ,  H03K5/13 ,  G11C13/00

CPC classification number: H03K5/13 ,  G11C11/5621 ,  G11C11/5642 ,  G11C16/32 ,  G11C2211/5644

Abstract: A timing circuit for reading from a device comprising multi-level non-volatile memory cells, which circuit comprises a single programmable delay block connected to an input terminal for memory address line transition signals. The delay block drives a counter which feedback controls the discharge through a combinational logic circuit connected to the output terminal of the programmable delay block. A logic output circuit, connected to the output terminal of the delay block and to the counter, generates the timing signals.

Abstract translation: 一种用于从包括多级非易失性存储器单元的器件读取的定时电路，该电路包括连接到用于存储器地址线转换信号的输入端的单个可编程延迟块。 延迟块驱动计数器，其反馈通过连接到可编程延迟块的输出端的组合逻辑电路来控制放电。 连接到延迟块的输出端和计数器的逻辑输出电路产生定时信号。

公开(公告)号：US5986411A

公开(公告)日：1999-11-16

申请号：US021289

申请日：1998-02-10

Applicant: Stefano Sueri ,  Atanasio La Barbera ,  Natale Aiello ,  Vito Graziano

Inventor： Stefano Sueri ,  Atanasio La Barbera ,  Natale Aiello ,  Vito Graziano

IPC: H03K17/30 ,  H05B41/282 ,  H05B37/02

CPC classification number: H03K17/30 ,  H05B41/2825 ,  Y10S315/07

Abstract: The present invention relates to an integrated circuit adapted to perform the function of a diode of the DIAC type, the circuit having an input terminal and an output terminal. The circuit includes a first input transistor having a first terminal connected to a fixed voltage reference, a second terminal, and a control terminal coupled to the input terminal of the circuit. The circuit further includes second and third transistors in a current mirror configuration, each having a first terminal for coupling to the input terminal of the circuit, and a second terminal, and associated control terminals connected together and coupled to the second terminal of the first input transistor, the second terminal of the second transistor being connected to the control terminal of the first transistor. Finally, the circuit includes a fourth output transistor connected, with first and second terminals, between the output terminal and the input terminal of the circuit, the fourth output transistor also having a control terminal connected to the second terminal of the third transistor.

Abstract translation: 本发明涉及一种适用于执行DIAC型二极管功能的集成电路，该电路具有输入端和输出端。 电路包括具有连接到固定电压基准的第一端子，第二端子和耦合到电路的输入端子的控制端子的第一输入晶体管。 电路还包括电流镜配置中的第二和第三晶体管，每个晶体管具有用于耦合到电路的输入端的第一端子和第二端子，以及连接在一起并耦合到第一输入端的第二端子的相关联的控制端子 晶体管，第二晶体管的第二端子连接到第一晶体管的控制端子。 最后，电路包括第四输出晶体管，与第一和第二端子连接在输出端子和电路的输入端之间，第四输出晶体管还具有连接到第三晶体管的第二端子的控制端子。

公开(公告)号：US5973966A

公开(公告)日：1999-10-26

申请号：US203798

申请日：1998-12-01

Applicant: Cristiano Calligaro ,  Paolo Rolandi ,  Roberto Gastaldi ,  Guido Torelli

Inventor： Cristiano Calligaro ,  Paolo Rolandi ,  Roberto Gastaldi ,  Guido Torelli

IPC: G11C11/413 ,  G11C7/06 ,  G11C11/56 ,  G11C16/06 ,  G11C16/04

CPC classification number: G11C7/062 ,  G11C11/5621 ,  G11C11/5642 ,  G11C7/065 ,  G11C7/06

Abstract: A read circuit for semiconductor memory cells, comprising first and second active elements coupled to a supply line via at least a first switch, wherein the first and second active elements are respectively connected, at first and second circuit nodes, respectively, to a first transistor through which the active elements are coupled to a ground. These first and second circuit nodes are also connected to ground through first and second capacitive elements, respectively, each having a switch connected in parallel to the capacitive element.

Abstract translation: 一种用于半导体存储器单元的读取电路，包括经由至少第一开关耦合到电源线的第一和第二有源元件，其中第一和第二有源元件分别在第一和第二电路节点连接到第一晶体管 有源元件通过它们耦合到地面。 这些第一和第二电路节点分别通过第一和第二电容元件连接到地，每个具有与电容元件并联连接的开关。

公开(公告)号：US5969408A

公开(公告)日：1999-10-19

申请号：US14364

申请日：1998-01-27

Applicant: Alberto Perelli

Inventor： Alberto Perelli

IPC: H01L21/31 ,  H01L21/316 ,  H01L23/00 ,  H01L23/31 ,  H01L23/532 ,  H01L23/544 ,  H01L23/58 ,  H01L29/06

CPC classification number: H01L23/564 ,  H01L23/3171 ,  H01L23/5329 ,  H01L2924/0002

Abstract: A process for the formation of a device edge morphological structure for protecting and sealing peripherally an electronic circuit integrated in a major surface of a substrate of semiconductor material includes formation above an intermediate process structure of a dielectric multilayer comprising a layer of amorphous planarizing material. The process also includes the partial removal of the dielectric multilayer so as to create at least one peripheral termination of the multilayer in the device edge morphological structure. Removal of the dielectric multilayer requires that the peripheral termination thereof be located in a zone of the intermediate process structure relatively higher than the level of the major surface, if compared with adjacent zones of the intermediate structure itself at least internally toward the circuit and in so far as to the device edge morphological structure.

Abstract translation: 用于形成用于在周围保护和密封集成在半导体材料的衬底的主表面中的电子电路的器件边缘形态结构的方法包括在包含非晶平坦化材料层的电介质多层的中间工艺结构之上形成。 该方法还包括部分去除电介质多层，以便在器件边缘形态结构中产生多层的至少一个外围终端。 如果与中间结构本身的相邻区域至少在内部朝向电路相比，去除电介质多层体需要其外围终端位于相对高于主表面的水平的中间工艺结构的区域中，并且如此 至于器件边缘的形态结构。

公开(公告)号：US5949666A

公开(公告)日：1999-09-07

申请号：US32282

申请日：1998-02-26

Applicant: Vincenzo Daniele ,  Alessandro Manstretta ,  Paolo Rolandi ,  Guido Torelli

Inventor： Vincenzo Daniele ,  Alessandro Manstretta ,  Paolo Rolandi ,  Guido Torelli

IPC: G05F1/46 ,  H03K4/02 ,  H02M1/12 ,  G05F1/40 ,  G05F7/64

CPC classification number: G05F1/465 ,  H03K4/023

Abstract: A staircase adaptive voltage generator circuit comprising a first capacitor connected between a first voltage reference and an output operational amplifier, through first and second switches, respectively. The terminals of the capacitor are also connected to a second voltage reference through third and fourth switches, respectively. A second capacitor, in series with a fifth switch, is connected in parallel to the first capacitor.

Abstract translation: 一种楼梯自适应电压发生器电路，包括分别通过第一和第二开关连接在第一电压基准和输出运算放大器之间的第一电容器。 电容器的端子也分别通过第三和第四开关连接到第二参考电压。 与第五开关串联的第二电容器与第一电容器并联连接。