公开(公告)号：US20060250852A1

公开(公告)日：2006-11-09

申请号：US11381426

申请日：2006-05-03

Applicant: Daniele Vimercati ,  Marco Onorato ,  Carmela Albano ,  Mounia El-Moutaouakil

Inventor： Daniele Vimercati ,  Marco Onorato ,  Carmela Albano ,  Mounia El-Moutaouakil

IPC: G11C11/34

CPC classification number: G11C8/10 ,  G11C8/14 ,  G11C11/5642 ,  G11C16/08 ,  G11C16/30

Abstract: A non-volatile memory device includes an array of memory cells organized into a plurality of array sectors, with each array sector being singularly addressable through an array wordline. An array of reference cells is addressable through a reference wordline. A respective voltage ramp generator is provided for each array sector for generating a voltage ramp on an array wordline for reading a memory cell therein, and is provided for each array of reference cells for generating a voltage ramp on a reference wordline for a reference cell therein. A respective row decoding circuit is coupled between each respective volage ramp generator and corresponding reference wordline or array wordline. A current generator generates a current to be injected on a circuit node in a selected array sector and on a circuit node of the array of reference cells to produce on the circuit nodes a voltage ramp similar to the generated voltage ramp. A respective local ramp generating circuit is prtovided for each array sector and for the array of reference cells, and delivering a charge current based upon a capacitance of the circuit nodes of the corresponding addressed array wordline or reference wordline, towards the respective row decoder of the wordline.

Abstract translation: 非易失性存储器件包括被组织成多个阵列扇区的存储器单元的阵列，每个阵列扇区通过阵列字线被单独寻址。 参考单元阵列可通过参考字线寻址。 为每个阵列扇区提供相应的电压斜坡发生器，用于在阵列字线上产生用于读取其中的存储单元的电压斜坡，并且为每个参考单元阵列提供参考单元阵列，用于在其上的参考单元的基准字线上产生电压斜坡 。 相应的行解码电路耦合在每个相应的电压斜坡发生器和相应的参考字线或阵列字线之间。 电流发生器产生要注入到选定的阵列扇区中的电路节点上的参考电池阵列的电路节点上的电流，以在电路节点上产生类似于所产生的电压斜坡的电压斜坡。 为每个阵列扇区和参考单元阵列提供相应的本地斜坡发生电路，并且将基于相应寻址的阵列字线或参考字线的电路节点的电容的充电电流分配给相应的行解码器 字线

公开(公告)号：US20060227609A1

公开(公告)日：2006-10-12

申请号：US11279378

申请日：2006-04-11

Applicant: Luigi Pascucci ,  Paolo Rolandi

Inventor： Luigi Pascucci ,  Paolo Rolandi

IPC: G11C16/04

CPC classification number: G11C16/08 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/12 ,  G11C16/24 ,  Y10T29/49002

Abstract: A non-volatile memory electronic device is integrated on a semiconductor with an architecture including at least one memory matrix organized in rows or word lines and columns or bit lines of memory cells. The matrix is divided into at least a first and a second memory portions having a different access speed. The first and second memory portions may share the structures of the bit lines which correspond to one another and one by one and are electrically interrupted by controlled switches placed between the first and the second portions.

Abstract translation: 非易失性存储器电子器件集成在具有包括以行或字线和存储器单元的列或位线组织的至少一个存储器矩阵的架构的半导体上。 矩阵被分成至少具有不同访问速度的第一和第二存储器部分。 第一和第二存储器部分可以共享彼此对应的位线的结构并且逐个地并且被放置在第一和第二部分之间的受控开关电中断。

公开(公告)号：US20060202245A1

公开(公告)日：2006-09-14

申请号：US11337787

申请日：2006-01-23

Applicant: Paola Zuliani ,  Fabio Pellizzer ,  Roberto Bez

Inventor： Paola Zuliani ,  Fabio Pellizzer ,  Roberto Bez

IPC: H01L29/94

CPC classification number: H01L27/2436 ,  H01L27/2472 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144

Abstract: A phase-change memory device, wherein memory cells form a memory array arranged in rows and columns. The memory cells are formed by a MOS selection device and a phase-change region connected to the selection device. The selection device is formed by first and second conductive regions which extend in a semiconductor substrate and are spaced from one another via a channel region, and by an isolated control region connected to a respective row and overlying the channel region. The first conductive region is connected to a connection line extending parallel to the rows, the second conductive region is connected to the phase-change region, and the phase-change region is connected to a respective column. The first connection line is a metal interconnection line and is connected to the first conductive region via a source-contact region made as point contact and distinct from the first connection line.

Abstract translation: 一种相变存储器件，其中存储器单元形成以行和列布置的存储器阵列。 存储单元由连接到选择装置的MOS选择装置和相变区域形成。 选择装置由在半导体衬底中延伸并且经由沟道区彼此间隔开的第一和第二导电区域以及连接到相应行并且覆盖沟道区域的隔离控制区域形成。 第一导电区域连接到与行平行延伸的连接线，第二导电区域连接到相变区域，并且相变区域连接到相应的列。 第一连接线是金属互连线，并且通过作为点接触而不同于第一连接线的源极接触区域连接到第一导电区域。

公开(公告)号：US20060171204A1

公开(公告)日：2006-08-03

申请号：US11241729

申请日：2005-09-30

Applicant: Nocola Del Gatto ,  Massimiliano Mollichelli ,  Massimiliano Scotti ,  Marco Sforzin

Inventor： Nocola Del Gatto ,  Massimiliano Mollichelli ,  Massimiliano Scotti ,  Marco Sforzin

IPC: G11C16/04

CPC classification number: G11C16/24 ,  G11C16/30

Abstract: A memory device has an array of memory cells. A column decoder is configured to address the memory cells. A charge-pump supply circuit generates a boosted supply voltage for the column decoder. A connecting stage is arranged between the supply circuit and the column decoder. The connecting stage switches between a high-impedance state and a low-impedance state, and is configured to switch into the high-impedance state in given operating conditions of the memory device, in particular during a reading step.

Abstract translation: 存储器件具有存储器单元阵列。 列解码器被配置为寻址存储器单元。 电荷泵供应电路为列解码器产生升压的电源电压。 连接级布置在电源电路和列解码器之间。 连接级在高阻抗状态和低阻抗状态之间切换，并且被配置为在存储器件的给定操作条件下，特别是在读取步骤期间切换到高阻抗状态。

公开(公告)号：US20060166439A1

公开(公告)日：2006-07-27

申请号：US11319750

申请日：2005-12-27

Applicant: Alessia Pavan ,  Giorgio Servalli ,  Cesare Clementi

Inventor： Alessia Pavan ,  Giorgio Servalli ,  Cesare Clementi

IPC: H01L21/336

CPC classification number: H01L27/11526 ,  H01L27/105 ,  H01L27/11539

Abstract: A method manufactures a non-volatile memory device on a semiconductor substrate that includes a matrix of memory cells and associated circuitry. The method includes: forming a filling dielectric layer on the whole substrate until gates of the cells and a conductive layer of the circuitry are completely covered, removing the dielectric layer until upper portions of the gates of the cells and the conductive layer are exposed, defining a plurality of gate electrodes of the transistors of the circuitry in the conductive layer, and forming source and drain regions of the transistors of the circuitry in the substrate. The method also comprises: forming spacers on side walls of gate electrodes of the transistors of the circuitry, and forming a silicide layer on the electrodes of the cells, on the gate electrodes of the transistors of the circuitry and on the source and drain regions of the transistors of said circuitry.

Abstract translation: 一种方法在包括存储器单元矩阵和相关电路的半导体衬底上制造非易失性存储器件。 该方法包括：在整个衬底上形成填充电介质层，直到电池的栅极和电路的导电层被完全覆盖，去除电介质层，直到电池的栅极和导电层的上部被暴露，限定 导电层中的电路的晶体管的多个栅电极，以及形成衬底中的电路的晶体管的源区和漏极区。 该方法还包括：在电路的晶体管的栅电极的侧壁上形成间隔物，并且在电路的电极上的栅电极上形成硅单元的电极上的硅化物层，并在电源的源极和漏极区 所述电路的晶体管。

公开(公告)号：US20060158928A1

公开(公告)日：2006-07-20

申请号：US11312253

申请日：2005-12-19

Applicant: Fabio Pellizzer ,  Agostino Pirovano

Inventor： Fabio Pellizzer ,  Agostino Pirovano

IPC: G11C11/00

CPC classification number: H01L27/2409 ,  G11C13/0016 ,  H01L27/2463 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1675

Abstract: A memory cell includes a memory element and a selection element coupled to said memory element. The selection element includes a first junction portion, having a first type of conductivity, and a second junction portion, having a second type of conductivity and forming a rectifying junction with the first junction portion. The first junction portion and the second junction portion are made of materials selected in the group consisting of: chalcogenides and conducting polymers.

Abstract translation: 存储单元包括存储元件和耦合到所述存储元件的选择元件。 选择元件包括具有第一类型的导电性的第一接合部分和具有第二类型导电性并与第一接合部分形成整流结的第二接合部分。 第一接合部分和第二接合部分由选自以下的材料制成：硫属化物和导电聚合物。

公开(公告)号：US20060149506A1

公开(公告)日：2006-07-06

申请号：US11294044

申请日：2005-12-05

Applicant: Giuseppe Cutuli ,  Francesco Imperiale ,  Roberto Lissoni ,  Mario Marchese

Inventor： Giuseppe Cutuli ,  Francesco Imperiale ,  Roberto Lissoni ,  Mario Marchese

IPC: G06F11/30

CPC classification number: G06F17/50 ,  G06F11/008

Abstract: A Design Failure Mode Effect Analysis (DFMEA) method analyzes faults and failures in the design phase of electronic devices. A data-entry mask is used for recording some information concerning the performed analysis and a portion of the recording form is displayed to a user in an electronic display format. The method detects and records past design problems and their corresponding solutions, by a DFMEA method using the data-entry mask form; associates keywords in a database with each problem; associates data concerning each of the design problems, in the same database, including information concerning past fails occurred in similar applications; detects major changes and/or innovations, as well as any improved block or part of a new device with respect to other devices, thereby postulating possible new problems introduced by the new device; and records the new problems and their possible solutions, by the DFMEA method and using the form.

公开(公告)号：US20060120136A1

公开(公告)日：2006-06-08

申请号：US11202428

申请日：2005-08-11

Applicant: Charles Dennison ,  Tyler Lowrey

Inventor： Charles Dennison ,  Tyler Lowrey

IPC: G11C11/00

CPC classification number: G11C11/22 ,  G11C5/063 ,  G11C11/16 ,  G11C13/0004 ,  G11C2213/79

Abstract: A crosspoint memory includes a shared address line. The shared address line may be coupled to cells above and below the address line in one embodiment. Voltage biasing may be utilized to select one cell, and to deselect another cell. In this way, each cell may be made up of a selection device and a crosspoint memory element in the same orientation. This may facilitate manufacturing and reduce costs in some embodiments.

Abstract translation: 交叉点存储器包括共享地址线。 在一个实施例中，共享地址线可以耦合到地址线上方和下方的单元。 可以使用电压偏置来选择一个单元，并且取消选择另一个单元。 以这种方式，每个单元可以由相同取向的选择装置和交叉点存储元件组成。 这在一些实施例中可以促进制造并降低成本。

公开(公告)号：US20060087261A1

公开(公告)日：2006-04-27

申请号：US11041519

申请日：2005-01-21

Applicant: Rosario Scollo ,  Marc Laudani ,  Antonino Gaito

Inventor： Rosario Scollo ,  Marc Laudani ,  Antonino Gaito

IPC: H05B41/36

CPC classification number: H02M1/4225 ,  G05F1/70 ,  Y02B70/126

Abstract: A method for controlling the power factor of a power supply line is described, the method using a power factor control cell connected to the power supply line. Advantageously according to the invention, the power factor control is performed by adjusting the turn-on and turn-off time of a bipolar transistor comprised in the power factor control cell. A cell for controlling the power factor of a power supply line is also described, of the type comprising a first and a second input terminals, a first and a second output terminals, the first input terminal being connected to the first output terminal by means of the series of an inductor and a diode, connected to each other in correspondence with an internal circuit node and the second input terminal and the second output terminal being connected to each other. Advantageously according to the invention, the control cell comprises a bipolar transistor inserted between the internal circuit node and the second input terminal and having a control terminal receiving a control signal derived from a signal having an elementary alternated trend.

Abstract translation: 描述了一种用于控制电源线的功率因数的方法，该方法使用连接到电源线的功率因数控制单元。 有利地，根据本发明，通过调整功率因数控制单元中包括的双极晶体管的接通和关断时间来执行功率因数控制。 还描述了用于控制电源线的功率因数的单元，其类型包括第一和第二输入端子，第一和第二输出端子，第一输入端子通过 与内部电路节点对应地连接的电感器和二极管的一系列，第二输入端子和第二输出端子彼此连接。 有利地，根据本发明，控制单元包括插入在内部电路节点和第二输入端子之间的双极晶体管，并且具有控制端子，其接收从具有基本交替趋势的信号导出的控制信号。

公开(公告)号：US20060083078A1

公开(公告)日：2006-04-20

申请号：US11250176

申请日：2005-10-13

Applicant: Marco Sforzin ,  Emanuele Confalonieri ,  Nicola Del Gatto ,  Carla Poidomani

Inventor： Marco Sforzin ,  Emanuele Confalonieri ,  Nicola Del Gatto ,  Carla Poidomani

IPC: G11C7/10

CPC classification number: G11C16/24 ,  G11C7/12 ,  G11C7/18 ,  G11C2207/002

Abstract: A semiconductor memory device is provided. The semiconductor memory device includes a memory matrix having a plurality of memory cells arranged according to a plurality of rows and a plurality of columns and a plurality of bit lines, each bit line being associated with at least one respective column of said plurality. The semiconductor memory device further includes a bit line selection structure for selecting at least one among said bit lines and a voltage clamping circuit structure adapted to cause the clamping at a prescribed voltage of unselected bit lines adjacent and capacitively coupled to a selected bit line during a read operation.

Abstract translation: 提供半导体存储器件。 半导体存储器件包括具有多个存储单元的存储器矩阵，存储器单元根据多个行排列，多个列和多个位线，每个位线与所述多个的至少一个相应的列相关联。 半导体存储器件还包括位线选择结构，用于选择所述位线中的至少一个和钳位电路结构，该钳位电路结构适于在一段时间内将与选定位线相邻且电容耦合的非选定位线的规定电压钳位 读操作。