公开(公告)号：US20240203907A1

公开(公告)日：2024-06-20

申请号：US18591881

申请日：2024-02-29

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Jiun Yi Wu ,  Chen-Hua Yu ,  Chung-Shi Liu

IPC分类号： H01L23/00 ,  H01L21/48 ,  H01L23/538 ,  H01L25/00 ,  H01L25/065

CPC分类号： H01L23/562 ,  H01L21/4853 ,  H01L21/4857 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5385 ,  H01L23/5386 ,  H01L24/16 ,  H01L25/0652 ,  H01L25/50 ,  H01L2224/16227 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/1427 ,  H01L2924/1437 ,  H01L2924/19103 ,  H01L2924/3511

摘要： In an embodiment, a structure includes a core substrate, a redistribution structure coupled, the redistribution structure including a plurality of redistribution layers, the plurality of redistribution layers comprising a dielectric layer and a metallization layer, a first local interconnect component embedded in a first redistribution layer of the plurality of redistribution layers, the first local interconnect component comprising conductive connectors, the conductive connectors being bonded to a metallization pattern of the first redistribution layer, the dielectric layer of the first redistribution layer encapsulating the first local interconnect component, a first integrated circuit die coupled to the redistribution structure, a second integrated circuit die coupled to the redistribution structure, an interconnect structure of the first local interconnect component electrically coupling the first integrated circuit die to the second integrated circuit die, and a set of conductive connectors coupled to a second side of the core substrate.

公开(公告)号：US20230207396A1

公开(公告)日：2023-06-29

申请号：US18178640

申请日：2023-03-06

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Wei-Min Liu ,  Hsueh-Chang Sung ,  Li-Li Su ,  Yee-Chia Yeo

IPC分类号： H01L21/8238 ,  H01L27/092 ,  H01L29/08 ,  H01L29/49 ,  H01L29/78 ,  H01L29/66

CPC分类号： H01L21/823864 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L27/0924 ,  H01L29/0847 ,  H01L29/4983 ,  H01L29/6656 ,  H01L29/7851 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/66795

摘要： A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.

公开(公告)号：US20220310815A1

公开(公告)日：2022-09-29

申请号：US17326848

申请日：2021-05-21

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Tze-Liang Lee

IPC分类号： H01L29/423 ,  H01L21/8234 ,  H01L29/417 ,  H01L29/66 ,  H01L29/78 ,  H01L29/40 ,  H01L27/088

摘要： A method includes depositing a dielectric layer, depositing a plurality of mandrel strips over the dielectric layer, and forming a plurality of spacers on sidewalls of the plurality of mandrel strips to form a plurality of mask groups. Each of the plurality of mandrel strips and two of the plurality of spacers form a mask group in the plurality of mask groups. The method further includes forming a mask strip connecting two neighboring mask groups in the plurality of mask groups, using the plurality of mask groups and the mask strip collectively as an etching mask to etch the dielectric layer and to form trenches in the dielectric layer, and filling a conductive material into the trenches to form a plurality of conductive features.

公开(公告)号：US20220171914A1

公开(公告)日：2022-06-02

申请号：US17672137

申请日：2022-02-15

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Ruey-Bin SHEEN ,  Tien-Chien HUANG ,  Chuan-Yao TAN

IPC分类号： G06F30/398 ,  G06F30/392 ,  G06F30/3953

摘要： The present disclosure describes an example method for cell placement in an integrated circuit (IC) layout design. The method includes defining a layout unit for a circuit implementation and arranging multiple layout units into a layout cell. The method also includes editing the layout cell to connect a first set of the layout units to be representative of the circuit implementation and to connect a second set of the layout units to be representative of a non-functional circuit. Further, the method includes inserting one or more dummy fill structures in areas of the layout cell unoccupied by the first and second sets of layout units.

公开(公告)号：US20210242150A1

公开(公告)日：2021-08-05

申请号：US17233967

申请日：2021-04-19

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Hui-Min Huang ,  Chih-Wei Lin ,  Tsai-Tsung Tsai ,  Ming-Da Cheng ,  Chung-Shi Liu ,  Chen-Hua Yu

IPC分类号： H01L23/00 ,  H01L23/538 ,  H01L23/31 ,  H01L21/56 ,  H01L21/48 ,  H01L23/498 ,  H01L23/48

摘要： A first protective layer is formed on a first die and a second die, and openings are formed within the first protective layer. The first die and the second die are encapsulated such that the encapsulant is thicker than the first die and the second die, and vias are formed within the openings. A redistribution layer can also be formed to extend over the encapsulant, and the first die may be separated from the second die.

公开(公告)号：US20200168527A1

公开(公告)日：2020-05-28

申请号：US16562540

申请日：2019-09-06

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Fong-Yuan CHANG ,  Chin-Chou LIU ,  Chin-Her CHIEN ,  Cheny-hung YEH ,  Hui Yu LEE ,  Po-Hsiang HUANG ,  Yi-Kan CHENG

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L27/06

摘要： A device, such as a computer system, includes an interconnection device die and at least two additional device dice. The additional device dies can be system on integrated chip (SOIC) dies laying face to face (F2F) on the interconnection device die. The interconnection device die includes electrical connectors on one surface, enabling connection to and/or among the additional device dice. The interconnection device die includes at least one redistribution circuit structure, which may be an integrated fan out (InFO) structure, and at least one through-silicon via (TSV). The TSV enables connection between a signal line, power line or ground line, from an opposite surface of the interconnection device die to the redistribution circuit structure and/or electrical connectors. At least one of the additional dice can be a three-dimensional integrated circuit (3DIC) die with face to back (F2B) stacking.

公开(公告)号：US08910101B1

公开(公告)日：2014-12-09

申请号：US14051522

申请日：2013-10-11

申请人： Taiwan Semiconductor Manufacturing Co., Ltd.

发明人： Chao-Yang Yeh ,  Cheng-Hung Yeh ,  Chi-Ting Huang

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F17/5031 ,  G06F17/5036 ,  H01L2224/73204

摘要： A method for determining an effective capacitance to facilitate a timing analysis using a processor generally comprises generating a model that is representative of a coupling between at least two TSVs. An impedance profile between the two TSVs as a function of at least one parameter is determined by using the model, wherein the impedance profile includes a plurality of impedance values corresponding to respective values of the parameter. An effective capacitance value corresponding to each respective impedance value is determined. An RC extraction is conducted of a design layout of a TSV circuit based on each determined effective capacitance value to generate an RC network.

摘要翻译： 用于确定有利电容以促进使用处理器的定时分析的方法通常包括生成代表至少两个TSV之间的耦合的模型。 通过使用该模型来确定作为至少一个参数的函数的两个TSV之间的阻抗曲线，其中阻抗分布包括对应于参数的相应值的多个阻抗值。 确定对应于各个阻抗值的有效电容值。 基于每个确定的有效电容值进行TSV电路的设计布局的RC提取以产生RC网络。

公开(公告)号：US20030013258A1

公开(公告)日：2003-01-16

申请号：US09904388

申请日：2001-07-12

申请人： Taiwan Semiconductor Manfacturing Co.,Ltd.

发明人： Fu-Sheng Lee

IPC分类号： H01L021/336

CPC分类号： H01L21/67294 ,  G03F1/40 ,  G03F7/70541 ,  G03F7/70741 ,  G03F7/70941 ,  H01L21/67353 ,  H01L21/67359 ,  H01L21/67396

摘要： An active anti-ESD pod for transporting photomask (reticle) comprises six body portions delimiting the container, an electrically conducting plate on the top portion, and an electrically conducting handle connected to the plate. An active charge sinker combined with a tag identifying the container or placed onto the photomask itself is provided to absorb the static electricity and to thus prevent charge accumulation that may otherwise cause ESD damage to the photomask.

摘要翻译： 用于传送光掩模（掩模版）的主动防静电盒包括限定容器的六个主体部分，顶部上的导电板和连接到该板的导电手柄。 提供与识别容器或放置在光掩模本身上的标签组合的有源电荷沉降片以吸收静电并因此防止否则可能对光掩模造成ESD损害的电荷累积。

公开(公告)号：US20240213330A1

公开(公告)日：2024-06-27

申请号：US18433872

申请日：2024-02-06

申请人： Taiwan Semiconductor Manfacturing Co., Ltd.

发明人： Chien-Wei Lee ,  Hsueh-Chang Sung ,  Yen-Ru Lee

IPC分类号： H01L29/165 ,  C30B25/10 ,  C30B25/12 ,  C30B25/16 ,  H01L21/02 ,  H01L21/324 ,  H01L29/417 ,  H01L29/66

CPC分类号： H01L29/165 ,  C30B25/10 ,  C30B25/12 ,  C30B25/165 ,  H01L21/02315 ,  H01L21/02658 ,  H01L21/02661 ,  H01L21/3247 ,  H01L29/41791 ,  H01L29/66636 ,  H01L29/66795

摘要： Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.

公开(公告)号：US20140231872A1

公开(公告)日：2014-08-21

申请号：US13771249

申请日：2013-02-20

申请人： TAIWAN SEMICONDUCTOR MANFACTURING CO., LTD.

发明人： Jean-Pierre Colinge ,  Kuo-Cheng Ching

IPC分类号： H01L29/78 ,  H01L29/66

CPC分类号： H01L29/7843 ,  H01L29/66795 ,  H01L29/7848 ,  H01L29/7849 ,  H01L29/785

摘要： FinFETs in which a swelled material within the fin, typically an oxide of the fin semiconductor, causes strain that significantly increases charge carrier mobility within the FinFET channel. The concept can be applied to either p-type or n-type FinFETs. For p-type FinFETs the swelled material is positioned underneath the source and drain regions. For n-type FinFETs the swelled material is positioned underneath the channel region. The swelled material can be used with or without strain-inducing epitaxy on the source and drain areas and can provide greater strain than is achievable by strain-inducing epitaxy alone.

摘要翻译： 翅片内部的膨胀材料（通常为散热片半导体的氧化物）的FinFET导致在FinFET通道内显着增加电荷载流子迁移率的应变。 该概念可以应用于p型或n型FinFET。 对于p型FinFET，膨胀材料位于源极和漏极区域的下方。 对于n型FinFET，膨胀的材料位于通道区域的下方。 溶胀材料可以在源极和漏极区域具有或不具有应变诱导外延使用，并且可以提供比单独应变诱导外延可实现的更大的应变。